In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL_12, LVTTL and LVCMOS (LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33). We have done power analysis of on-chip power like clock power, signals power, IO power, leakage power and supply power. We notified our analysis at five different voltages like 0.5V,
In this work, we are going to use thermal aware approach in Encoder design and also testing thermal stability by working on different ambient temperatures 298.
In this paper an approach is made to design Pseudo open drain IO standards Based Energy efficient solar charge sensor design on 20nm and 28nm technology. We have used LVCMOS18, POD10, POD10_DCI and POD12 I/O standard. In this design, we have taken two main parameters for analysis that are frequencies (GHz) and AIRFLOW. We have taken one value for LFM i.e. 250 and Medium as a default profile for heat sink and constant environment. For the simulation of the logic, Xilinx is used with Verilog as hardware description language. We have done our analysis for different frequency values for POD based solar charge inverter. We also observed maximum total power reduction in LVCMOS18 (Artix-7 FPGA) as compared to other I/O standards at 10 GHz. Also there is maximum total power reduction in POD12 (Ultra Scale Kintex) as compared to other I/O standards at 2 GHz. There is also a significant change in device static, I/O power and Clock Power.
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