In this paper, we present a formal equivalence checking method for source-to-source refinements in C-based high-level hardware design descriptions. The method is based on word-level symbolic simulation, where variables and operators in designs are treated as uninterpreted symbols. In addition, we introduce a more efficient method utilizing the difference between two designs under verification. It can verify the equivalence faster when the similarity between the designs is large. We also show case studies of equivalence checking that were carried out with our verification framework FLEC.
When designing today's highly complicated systems consisting of several hardware and software modules, it is essential to estimate the performance such as worst-case or best-case execution time in early design stages. Such estimation is essential to explore architecture and hardware/software partitioning in system-level design. A maximum execution time estimated topologically without considering false-paths is longer than the real. In this paper, we propose an static estimation method of maximum execution time in system-level designs, considering false-paths. Also, we adopt an approximation approach in order to avoid the path explosion problem. The experimental results show that our method can provide much smaller estimated maximum execution time than the method without considering false-paths. At the same time, the results show us that the maximum execution time can be estimated to a very small range, by applying both simulation-based method and our static method.
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