Equivalence checking of high-level designs based on symbolic simulation

Abstract

In this paper, we present a formal equivalence checking method for source-to-source refinements in C-based high-level hardware design descriptions. The method is based on word-level symbolic simulation, where variables and operators in designs are treated as uninterpreted symbols. In addition, we introduce a more efficient method utilizing the difference between two designs under verification. It can verify the equivalence faster when the similarity between the designs is large. We also show case studies of equivalence checking that were carried out with our verification framework FLEC.

Equivalence checking between SLM and RTL using machine learning techniques

“…Zhu et al [8] proposed a technique to further decompose the verification problem in both the space and the time dimension and used an SMT solver to check the sequential compare points. Ta keshi Matsumoto et al detected and extracted texture difference of two designs, and checked the equivalence of differences by symbolic simulation [9]. There are some works aimed at checking the equivalence between designs at different stages in high-level synthesis (HLS) [10], [11], [12].…”