Synthesis and formal verification of on-chip protocol transducers through decomposed specification

Fujita, Masahiro; Tanida, Hideo; Gao, Fei; Nishihara, Tasuku; Matsumoto, Takeshi

doi:10.1109/isqed.2010.5450526

Cited by 3 publications

(7 citation statements)

References 2 publications

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“…Transducers, generated using transducer synthesis techniques [Fujita et al 2010;Watanabe et al 2007;Gerstlauer et al 2007], include additional functionality to store and forward data packets between bus protocols. In Fujita et al [2010] and Watanabe et al [2007], protocol pairs are first categorised into four types based on the kind of operations they support. The identified type is used to generate an associated datapath, while the composition of the given protocol pair is pruned to create a transducer with minimum latency.…”

Section: Converter Generation Algorithmsmentioning

confidence: 99%

“…All protocol conversion techniques compute a product of given protocols and then prune execution paths that violate requirements from the product [Kumar and Nelvagal 1996;Passerone et al 2002;Avnit et al 2009;Fujita et al 2010]. Protocol conversion is related to the problem of discrete controller synthesis, where a controller is automatically generated to control a plant and avoid infeasible paths [Gierds et al 2012;Kumar et al 1997].…”

Section: Converter Generation Algorithmsmentioning

confidence: 99%

“…Existing protocol conversion techniques can be categorised into three types. Transaction relation and refinement approaches check compatibility between protocols so that protocols can progress collectively and deadlocks can be avoided [D'Silva et al 2005;Roop et al 2009;Avnit et al 2009;Fujita et al 2010]. In Avnit et al [2009], the absence of a transaction relation between two IP protocols signifies the presence of mismatches, and automatically generated converters try to enforce compatibility between protocols.…”

Section: Converter Generation Algorithmsmentioning

confidence: 99%

See 2 more Smart Citations

A Formal Approach to Incremental Converter Synthesis for System-on-Chip Design

Sinha

Girault

Goessler

et al. 2014

ACM Trans. Des. Autom. Electron. Syst.

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A system-on-chip (SoC) contains numerous intellectual property blocks, or IPs. Protocol mismatches between IPs may affect the system-level functionality of the SoC. Mismatches are addressed by introducing converters to control inter-IP interactions. Current approaches towards converter generation find limited practical application as they use restrictive models, lack formal rigour, handle a small subset of commonly encountered mismatches, and/or are not scalable. We propose a formal technique for SoC design using incremental converter synthesis. The proposed formulation provides precise models for protocols and requirements, and provides a scalable algorithm that allows adding multiple components and requirements to an SoC incrementally. We prove that the technique is sound and complete. Experimental results obtained using real-life AMBA benchmarks show the scalability and wide range of mismatches handled by our approach. . 2014. A formal approach to incremental converter synthesis for system-on-chip design.

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Section: Converter Generation Algorithmsmentioning

confidence: 99%

Section: Converter Generation Algorithmsmentioning

confidence: 99%

Section: Converter Generation Algorithmsmentioning

confidence: 99%

See 1 more Smart Citation

A Formal Approach to Incremental Converter Synthesis for System-on-Chip Design

Sinha

Girault

Goessler

et al. 2014

ACM Trans. Des. Autom. Electron. Syst.

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“…Sometimes, IPs may suffer from protocol mismatches and fail to communicate and/or meet system-level requirements. We can manually modify IPs, or use layer-specific IPs like bridges at the data-link layer or transducers at the network layer [3]. Formal protocol conversion algorithms like [4]- [7] can automatically generate IPs called converters that guarantee that the system will satisfy implicit or user-specified requirements.…”

Section: Introductionmentioning

confidence: 99%

“…We focus only on the processor and deinterlacer IPs in this paper, without losing the generality of the framework. IP protocols are modelled using labelled transition systems, similar to existing protocol conversion approaches [3]- [5], [7].…”

Section: Introductionmentioning

confidence: 99%

Conversing at Many Layers: Multi-layer System-on-Chip Protocol Conversion

Sinha

2015

2015 20th International Conference on Engineering of Complex Computer Systems (ICECCS)

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The numerous intellectual property blocks of a system-on-a-chip must be integrated so that they can meet system-specific requirements. However, such integration is not guaranteed due to mismatches between IP protocols. Protocol conversion algorithms can generate converters that can guarantee correct system behaviour, but the implementation of converters on-chip remains an open question. IPs can be modelled at several layers of the Open Systems Interconnection (OSI) model. Current protocol conversion algorithms either focus on a single layer or worse, blur the boundaries between these layers. We propose a formal framework that allows generating implementable converters for IP protocols modelled at different OSI layers using any existing converter generation algorithm. We apply the framework to an existing conversion algorithm and discuss how it can be as readily used with other algorithms.

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