This paper proposes a jitter suppression technique for a highspeed interface macro by decreasing the disturbance onto a power node of the macro. The power node fluctuates in accordance with the output data pattern from the macro. Namely, it becomes lower at the dense data pattern and returns near to an initial value at the sparse data pattern. This fluctuation causes the jitter and deteriorates the data eye on the output node. The proposed scheme relaxes the dense and sparse pattern dependency by decreasing the fluctuation. Simulation results show a significant suppression of i) the power node fluctuation from 20 mV to 8 mV, and ii) the jitter from 160 ps to 60 ps on the data eye. Clear data eye openings were obtained at various data rates on actual measurements.
This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and onchip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of V dd and it provides 91 times better failure rate with a 35% droop of V dd compared with the conventional design.
This paper proposes an ultra-wide range transmitter with a latched AC-coupled driver (LACD) and a dummy data transient generator (DDTG). The LACD expands the low-frequency range by preventing the capacitor discharge issue of the high-speed AC-coupled driver and the DDTG enhances the high-frequency range by generating a dummy transient pattern to stabilize the power node fluctuation induced by the dense and sparse pattern dependency in the case of coding-less application. A 24-channel test chip designed with 40-nm CMOS technology achieved an ultrawide frequency range (0.01-10 Gbps/channel) and ultra-wide bandwidth from 0.01 Gbps (0.01 Gbps × 1 channel) to 240 Gbps (10 Gbs × 24 channels) and a high area efficiency (0.0027 mm 2 /Gbps/channel). At the data rates of 5 and 10 Gbps, the jitters with DDTG were 50% lower than attained without DDTG.
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