A jitter suppression technique against data pattern dependency on high-speed interfaces for highly integrated SoCs

Abstract

This paper proposes a jitter suppression technique for a highspeed interface macro by decreasing the disturbance onto a power node of the macro. The power node fluctuates in accordance with the output data pattern from the macro. Namely, it becomes lower at the dense data pattern and returns near to an initial value at the sparse data pattern. This fluctuation causes the jitter and deteriorates the data eye on the output node. The proposed scheme relaxes the dense and sparse pattern dependency by decreasing the fluctuation. Simulation results show a significant suppression of i) the power node fluctuation from 20 mV to 8 mV, and ii) the jitter from 160 ps to 60 ps on the data eye. Clear data eye openings were obtained at various data rates on actual measurements.

An ultra-wide range (0.01–240 Gbps) transmitter with latched AC-coupled driver and dummy data transient generator

“…In order to reduce the jitter caused by the pattern-dependency, we employ the Data Transient Generator (DTG) in [12]. In this paper, we call DTG a DDTG (Dummy Data Transient Generator).…”

“…The circuit and timing chart of the DDTG shown in Fig. 8 are essentially the same as the DTG in [12].…”

“…For the first time in this paper, we have designed the DDTG that can operate at 24 channels. The DTG in [12] was used for only 8 channels. …”