The 42 amino acid form of beta amyloid (Abeta42) plays a pivotal role in neurotoxicity and the activation of mononuclear phagocytes in Alzheimer's disease (AD). Our recent study revealed that FPRL1, a G-protein-coupled receptor, mediates the chemotactic and activating effect of Abeta42 on mononuclear phagocytes (monocytes and microglia), suggesting that FPRL1 may be involved in the proinflammatory responses in AD. We investigated the role of FPRL1 in cellular uptake and the subsequent fibrillar formation of Abeta42 by using fluorescence confocal microscopy. We found that upon incubation with macrophages or HEK293 cells genetically engineered to express FPRL1, Abeta42 associated with FPRL1 and the Abeta42/FPRL1 complexes were rapidly internalized into the cytoplasmic compartment. The maximal internalization of Abeta42/FPRL1 complexes occurred by 30 min after incubation. Removal of free Abeta42 from culture supernatants at 30 min resulted in a progressive recycling of FPRL1 to the cell surface and degradation of the internalized Abeta42. However, persistent exposure of the cells to Abeta42 over 24 h resulted in retention of Abeta42/FPRL1 complexes in the cytoplasmic compartment and the formation of Congo red positive fibrils in macrophages but not in HEK 293 cell transfected with FPRL1. These results suggest that besides mediating the proinflammatory activity of Abeta42, FPRL1 is also involved in the internalization of Abeta42, which culminates in the formation of fibrils only in macrophages.

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A single-chip H.264/MPEG-4 audiovisual LSI for mobile applications including terrestrial digital broadcasting systems such as ISDB-T and DVB-H with a module-wise dynamic voltage/frequency scaling architecture is fabricated in a 90nm 6M CMOS technology. This LSI operates even during the voltage/frequency transition, so there is no performance overhead. Voltage/frequency scaling is realized by a dynamic deskewing system and an on-chip voltage regulator with slew rate control. Figure 7.3.1 shows a micrograph of the chip equipped with four optimally configured RISC processors, dedicated hardware accelerators for specific signal processing, 32Mb embedded DRAM and interfaces for camera, display, audio and network streaming for mobile multimedia applications. The power consumed when decoding QVGA (320x240) H.264 baseline profile level 1.2 video streams at 15frames/s and MPEG-4 AAC LC is only 90mW. The chip features are summarized Fig. 7.3.2.H.264 and MPEG-4 standards play essential roles in the field of mobile multimedia. H.264 is a video compression standard adopted for terrestrial digital broadcasting. Demands for larger image size, higher frame rate and higher image quality are ever increasing. These demands require larger memory capacity and higher operating frequency, both resulting in higher power consumption, which is unacceptable for battery-powered mobile equipments. The LSI described in this paper decodes CIF (352x288) H.264 baseline profile at level 2, or encodes VGA (640x480) MPEG-4 SP @L4a video stream at 30 frames/s while encoding/decoding audio/speech streams and multiplexing/demultiplexing them at 180MHz. Figure 7.3.3 shows the block diagram of the chip.There are four major modules: video frontend, video backend, audio/speech and multiplexer/demultiplexer. Each of the modules consists of an optimally configured 32b media-embedded processor (MeP) core [1] and dedicated hardware accelerators for its specific operation. These modules, peripheral interface units for camera, display, mic/speaker, network, etc. and embedded DRAM are connected via a 64b main bus. As for voltage and frequency, this chip slows down the audio module independently from the rest of the chip. The audio module is decoupled by a voltage/frequency socket from the main bus and an on-chip voltage regulator and a dynamic deskewing system (DDS) for the dynamic voltage/frequency scaling.H.264, compared to previous video standards, requires very high programmability so it is very difficult to implement in dedicated hardware accelerators. By studying data processing procedures, elementary processes, are allocated to the processor core or the hardware accelerators, including a context adaptive variable length decoder. Cooperation between the processor core and dedicated hardware accelerators have successfully reduced a large amount of operation time and power consumption without losing the programmability necessary for H.264. Traditional power reducing techniques such as embedded DRAM, clock gating and gated I/O are implemented as in previous w...

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