Geyser-2: The second prototype CPU with fine-grained run-time power gating

Zhao, Xiujian; Ikebuchi,; Saito,; Kamata,; Seki,; Kojima,; Amano,; Koyama,; Hashida,; Umahashi,; Masuda,; Usami,; Kimura,; Namiki,; Takeda,; Nakamura,; Kondo,

doi:10.1109/aspdac.2011.5722310

Cited by 7 publications

(8 citation statements)

References 2 publications

(3 reference statements)

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“…EXEC: The EXEC units in the FU array are used for acceleration under the Array Execution. For a known DFG, only necessary FUs need to be active while the other parts can easily be put into power OFF state by PG, following the same scheme as in paper [9]. The prefetch time span overlaps and conceals the wakeup time span of the execution unit, as shown in Fig.…”

Section: If Idmentioning

confidence: 99%

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A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction

Nakashima

Devisetti

et al. 2014

IEICE Trans. Inf. & Syst.

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SUMMARYGeneral purpose many-core architecture (MCA) such as GPGPU has recently been used widely to continue the performance scaling when the continuous increase in the working frequency has approached the manufacturing limitation. However, both the general purpose MCA and its building block general purpose processor (GPP) lack a tuning capability to boost energy efficiency for individual applications, especially computation intensive applications. As an alternative to the above MCA platforms, we propose in this paper our LAPP (Linear Array Pipeline) architecture, which takes a special-purpose reconfigurable structure for an optimal MIPS/W. However, we also keep the backward binary compatibility, which is not featured in most special hardware. More specifically, we used a general purpose VLIW processor, interpreting a commercial VLIW ISA, as the baseline frontend part to provide the backward binary compatibility. We also extended the functional unit (FU) stage into an FU array to form the reconfigurable backend for efficient execution of program hotspots to exploit parallelism. The hardware modules in this general purpose reconfigurable architecture have been locally zoned into several groups to apply preferable low-power techniques according to the module hardware features. Our results show that under a comparable performance, the tightly coupled general/special purpose hardware, which is based on a 180nm cell library, can achieve 10.8 times the MIPS/W of MCA architecture of the same technology features. When a 65 technology node is assumed, a similar 9.4x MIPS/W can be achieved by using the LAPP without changing program binaries.

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Section: If Idmentioning

confidence: 99%

“…Other stages (i.e., excluding VLIW stage) in the LAPP contain only EXEC, MAP, SEL, an LSU and an L0$ buffer. Finally, the circuit size of the power gating circuit (PGC) is calculated as 15% of the total area [9].…”

Section: Circuit Sizementioning

confidence: 99%

A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction

Nakashima

Devisetti

et al. 2014

IEICE Trans. Inf. & Syst.

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“…Recently, however, fine-grain power gating receives much attention because finer granularity increases the chances of PG. For example, Geyser-2 [2] and Geyser-3 [3] implement a fine-grained run-time PG. In these processors, PG is applied to function units (FUs).…”

Section: Low Power Techniquesmentioning

confidence: 99%

“…As static power is consumed without any contribution to computing, its reduction is strongly required. A wide variety of power reduction techniques has been proposed and realized, including clock gating, power gating, DVFS, and so 1 The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan 2 Renesas Electronics Corporation, Chiyoda, Tokyo 100-0004, Japan †1…”

Section: Introductionmentioning

confidence: 99%

Design Aid of Multi-core Embedded Systems with Energy Model

Nakada

Okamoto

Komoda

et al. 2014

IPSJ Online Transactions

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Shifting to multi-core designs is so pervasive a trend to overcome the power wall and it is a necessary move for embedded systems in our rapidly evolving information society. Meanwhile, the need to increase the battery life and reduce maintenance costs for such embedded systems is very critical. Therefore, a wide variety of power reduction techniques have been proposed and realized, including Clock Gating, DVFS and Power Gating. To maximize the effectiveness of these techniques, task scheduling is a key but for multi-core systems it is very complicated due to the huge exploration space. This problem is a major obstacle for further power reduction. To cope with it, we propose a design method for embedded systems to minimize their energy consumption under performance constraints. This method is based on the clarification of properties of the above mentioned low power techniques and their interactions. In more details, we firstly establish energy models for these low power techniques and our target systems. We then explore for the best configuration by constructing an optimization problem especially for applications which have a longer deadline than the execution interval. Finally, we propose an approximate solution using dynamic programming with a lower computation complexity and compare it to a brute force explicit solution. We confirm with our evaluations that the proposed method successfully found a better configuration which reduces the total energy consumption by 32% if compared to the manually optimized configuration, which utilizes only one core.

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“…It consists of a low-power microprocessor called Geyser [9] and coarse grained accelerators called CMACube [10] connected with the wireless inductive coupling Thru-Chip Interface (TCI). In Cube-1, a uni-directional ring network with bubble-flow control [11] is formed just by stacking chips.…”

Section: Introductionmentioning

confidence: 99%

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Nomura

Matsushita

Kadomoto

et al. 2018

IJNC

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A wireless inductive coupling ThruChip Interface (TCI) is a flexible system-in-package (SiP) technique which enables to build a powerful interconnection network between stacked chips. For easy use of TCI, we have developed intellectual properties (IPs), and proposed an interconnection network which can make the use of IPs. We also developed a real chip embedded the IP, and evaluated the performance. By stacking multiple chips with the proposed IP, an inter-chip network with link-to-link flow control by piggyback control is established. The new proposed escalator network which uses piggyback of the credit packets outperforms the ring network used in the first prototype by 28%-59% in terms of throughput. The performance overhead by the piggyback control was less than 3%-4% of that without control messages.

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Geyser-2: The second prototype CPU with fine-grained run-time power gating

Cited by 7 publications

References 2 publications

A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction

A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction

Design Aid of Multi-core Embedded Systems with Energy Model

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

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