A new 5V 0.8 um CMOS technology merges IOOK custom circuits and 4.5 M DRAMonto a single die that supports both high density memory and significant computing logic. One of the j r s t chips built with this technology implements a unique Processor-In-Memory (PIW computer architecture termed EXECUBE, and has 8 separate 25 MHz CPU macros and 16 separate 32Ki9b DRAM mucros on a single die. These macros are organized together to provide a single part type for scaleable massively parallel processing applications, particularly embedded ones where minimal glue logic is desired. Each chip delivers 50 Mips ofperformance at 2.7W.This paper overviews the basic chip technology and organization, some projections on the future of EXECUBE-like PIM chips, and finally some lessons to be learned as to why this technology should radically afSect the way we ought think about computer architecture.
We present a systematic study of an anomalous charge leakage phenomenon in Flash memories which occurs at temperatures below 150C. Essential characteristics of the leakage are described in association with various process parameters. A new leakage mechanism based on diffusion of an ionic entity produced by regenerative electrochemical reactions through percolating networks in the silicon dioxide is proposed.
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