A new electron beam reticle writing system has been developed for a 16-256M dynamic random access memory (DRAM) class reticle pattern making. A continuously moving stage, variable-shaped beam and vector-scanning method has been adopted. The acceleration voltage was varied from 20 to 12.5 kV. An acceleration voltage of 15 kV provided proximity effect correction free exposure for reticle patterns larger than 2 μm corresponding to the minimum feature size of 16M DRAM class devices. A single reticle processing autoloader has also been developed for quick turn around time. Parallel processing of data conversion has enabled the system to convert Gaussian beam system data to the new variable shaped beam system data of 10 MB volume in about 20 min.
Below 40nm design node, systematic variation due to lithography must be taken into consideration during the early stage of design. So far, litho-aware design using lithography simulation models has been widely applied to assure that designs are printed on silicon without any error.However, the lithography simulation approach is very time consuming, and under time-to-market pressure, repetitive redesign by this approach may result in the missing of the market window.This paper proposes a fast hotspot detection support method by flexible and intelligent vision system image pattern recognition based on Higher-Order Local Autocorrelation. Our method learns the geometrical properties of the given design data without any defects as normal patterns, and automatically detects the design patterns with hotspots from the test data as abnormal patterns. The Higher-Order Local Autocorrelation method can extract features from the graphic image of design pattern, and computational cost of the extraction is constant regardless of the number of design pattern polygons.This approach can reduce turnaround time (TAT) dramatically only on 1CPU, compared with the conventional simulation-based approach, and by distributed processing, this has proven to deliver linear scalability with each additional CPU.
A new high-speed electron beam (EB) data conversion system has been developed for the variable-shaped beam EB reticle writing system EX-8. The target conversion rate from computer-aided design (CAD) data to EX-8 data is five reticles per hour for the class of 16-Mbit dynamic random access memory (DRAM) and beyond. To achieve this, both the hierarchical and parallel shape data operations and the parallel EB formatting have been adopted. Preprocesses for the hierarchical operations have been integrated, such as cell-overlap eliminations and the “doughnut process” which involves partially expanding shapes near cell boundaries. A 64-Mb DRAM design was successfully converted in the hierarchical method on an engineering workstation (EWS) with a single processor, and the number of processed shapes was reduced by four orders of magnitude and the average processing time was less than nine minutes. The processing time of the shape data operations for one layer of a 129 k gate array was reduced to 1/3 when four processes were performed in parallel on an EWS with four processors.
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