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A low phase noise VCO with bond wire inductor for DVB‐H is implemented in TSMC CMOS 0.18 μm. The bond wire VCO exhibits −137 dBc/Hz at 1 MHz with the 5 mA current consumption. To meet the DVB‐H phase noise requirement, bond wire modeling is introduced in this paper. Due to the bond wire characteristics, Q value of the VCO inductor is more than 25 at 1 GHz. The proposed wire bond inductor provides an additional frequency tuning option after IC fabrication by modifying the length of the wire bond. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 859–863, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23228

Due to insufficient stability of the four-channel system, some measurements were taken in a simplified system with only two MIMO channels. The numbers of transmitting lasers and receiving channels were reduced to two, and 4 Â 4 couplers/splitters were replaced with 2 Â 2 elements, but otherwise the system was similar to that presented in Figure 2. The 2 Â 2 system operated much more stable than 4 Â 4 setup, and its tuning was far more easier. In this two-channel system, we measured the influence of the carrier frequency selection on the quality of the received signals expressed by Q parameter. This relation for both channels is shown in Figure 5 for carrier frequencies in the range of 0.5-1 GHz. It is readily seen that the carrier frequency only weakly affects the received signals quality (Q parameter) over the measured range. It is worth mentioning that this range was well above the 3 dB base-band width, which was around 150 MHz in this case. This is consistent with the results of Ref. 8, where it was indicated that channel SNR is relatively immune to the carrier changes. This occurs despite the fact that the frequency transfer function between ports has a character typical for SCM transmission with pass-bands separated by dips (see example in Fig. 6). The relative immunity of SNR/eye pattern/Q parameter to the carrier frequency selection is due to fact that at the frequency response dips, the phase of the frequency response varies significantly decorrelating the elements of the matrix [h ij ] and compensating at least partially for the greater signal attenuation.Obviously, any practical realization of MIMO transmission should involve an automatic algorithm for the transmission matrix inversion. In this work, this operation was performed manually, which turned out to be very cumbersome for four-channel system. CONCLUSIONSABSTRACT: This letter presents a design methodology for the millimeter wave amplifier using 90-nm Taiwan Semiconductor Manufacture Company (TSMC) CMOS technology. The proposed design scheme with mathematically modeled transmission lines and interstage matching transformers illustrates how to design a millimeter amplifier considered in the maximum power transfer. The single-ended transformer-coupled CMOS PA is implemented to verify the design methodology. The design consists of neutralized common source (CS) amplifiers, matching transmission lines, and 3D modeled transformers. The designed circuit shows 16.2-dB gain and 9-dBm saturation power over 60-GHz channel. The measured results are well matched with the proposed modeling results.

This paper presents a novel on chip transformer coupled PA (Power Amplifier) in a 9 Metal Generic 90-nm TSMC CMOS technology for the 60 GHz mm-Wave (millimetre wave) WPAN. The PA consists of three stage CS (Common Source) amplifiers and inter-stage matching transformers. The architecture of the transformer is a stacked-structure which provides high coupling coefficient with a relatively small size. The transformer's parameters are simulated by the 3-D electromagnetic simulator. To enhance the gain and linearity of the PA, the miller capacitance neutralized technique is adopted in this paper. The designed PA shows maximum 26.5 dB gain over 3 dB frequency 58.6 ~ 63.6 GHz. The output 1 dB compression point is 12.1 dBm, and the output saturation power is 14.46 dBm under 1.2V supply voltage. The PAE(Power Added Efficiency) of the circuit is 12.48 %. All the results of this paper are excellent comparing to previous work.

This paper proposes a new all digital phase-locked loop (ADPLL) which operates from 80MHz to 800MHz with the locking cycle of less than 40 clock cycles. It employs a time measurable digital controlled oscillator (TMDCO), which helps the reduction of locking cycle. The proposed ADPLL adopts the (8+4)-bit TMDCO and is very insensitive to its linearity and monotonicity characteristics. The validity of the approach is clearly proved by both the analytic method and spectre simulations in a 90-nm fabrication technology.

This paper proposes a high efficiency power amplifier with a diode linearizer and voltage combining transformers in a standard 0.13-μm TSMC CMOS technology. The 3-D simulated transformer adopts multi-finger architecture which provides low insertion loss and allows high current capacity on the transformer. With the 4 differentially cascaded connected multi-finger transformers, the amplifier delivers more than 1W output power under 1.8 V supply condition. To enhance linearity of the power amplifier, the diode configuration bias circuit is used in this paper. With all integration of transformers, balun, diode bias circuits and same 4 diff-amps, the prototype Class AB Power Amplifier shows 32dBm saturation power at 2.4 GHz. Due to the diode linearizer the output P1dB is 30.8 dBm with 28 % Power Added Efficiency.