The authors thank the correspondents for their note. The c 2 0 =2 correction term, while valid, rarely plays an important role in the final result because normally c 2 0 =2 is much smaller than 0 2 rms . The worst case scenario (which does not normally happen) is constant impulse sensitivity function (ISF). In this case, 0rms = c0. Correction to "A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC"Kong-Pang Pun, Shouri Chatterjee, and Peter KingetIn the above paper [1], a mistake in the schematic diagram of the 0.5-V operational transconductance amplifier (OTA) (Fig. 11) was discovered by Prof. Dr. Martin Schubert of FH Regensburg, University of Applied Sciences, Regensburg, Germany. The original OTA circuit diagram shows two series combinations of a 5-k resistor and a 20-pF capacitor connecting the outputs of the first stage to the inputs of the second stage, which is incorrect. The correct OTA schematic is shown in Fig. 1 below. The RC combinations are connected between the inputs and outputs of the second stage for Miller compensation with right-half-plane zero cancellation and the first and second stages are directly coupled. We apologize for this error.

Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near min by choosing an appropriate device geometry along with an optimal bias condition. An 800-MHz LNA has been implemented in a standard 0.24m CMOS technology. The amplifier possesses a 0.9-dB noise figure with a 7.1-dBm third-order input intercept point, while drawing 7.5 mW from a 2.0-V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.