A noise optimization technique for integrated low-noise amplifiers

Abstract

Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near min by choosing an appropriate device geometry along with an optimal bias condition. An 800-MHz LNA has been implemented in a standard 0.24m CMOS technology. The amplifier possesses a 0.9-dB noise figure with a 7.1-dBm third-order input intercept point, while drawing 7.5 mW from a 2.0-V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.

SET analysis and radiation hardening techniques for CMOS LNA topologies

“…However, under low power consumption conditions, the required inductance value to obtain adequate noise and input matching is very large. This results in a minimum achievable NF of the LNA significantly higher than its NF min [23]. This can be solved by adding the C ex capacitor shown in figure 8 [24].…”

Two different LNA optimizing techniques

“…These equations are also based on noise parameters. However, as we will discuss later, both References [7] and [9] neglect the parasitic capacitor C gd (or C bc /, which can result in large deviations for bipolar LNAs, because a BJT typically exhibits a larger ratio of C bc and C be , as compared to MOSTs. When the frequency goes higher, however, the deviations are also significant even in CMOS LNAs.…”