Articles you may be interested inChemical mechanical polishing of shallow trench isolation using the ceria-based high selectivity slurry for sub-0.18 μm complementary metal-oxide-semiconductor fabrication Critical dimension control optimization methodology on shallow trench isolation substrate for sub-0.25 μm technology gate patterning Plasma etch-back planarization coupled to chemical mechanical polishing for sub 0.18 μm shallow trench isolation technologyThe resultant surface microscratches due to chemical mechanical polishing ͑CMP͒ can cause device failure and reduce production yield in the shallow trench isolation ͑STI͒ process. By using a plasma etch process to replace the overpolish step of CMP planarization (CMPϩplasma etch͒, we have reduced 10% of the total defect counts in the 0.15 m STI process. The CMP microscratches have been effectively smoothened by the additional plasma etch process. The electrical properties of the devices made via the CMP and the CMPϩplasma etch processes have been examined and compared. The off-state currents are similar. A higher breakdown voltage is found for the CMP ϩplasma etch process and can be interpreted by the local electrical-field concentration. Although the n ϩ / p and p ϩ /n junctions fabricated by the CMPϩplasma etch processes exhibit slightly larger leakage currents for certain test patterns, due to plasma damage, the products still meet the inline production requirements, and show promising results for yield improvement.
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