Chemical mechanical polishing defect reduction via a plasma etch in the 0.15 μm shallow trench isolation process

Abstract

Articles you may be interested inChemical mechanical polishing of shallow trench isolation using the ceria-based high selectivity slurry for sub-0.18 μm complementary metal-oxide-semiconductor fabrication Critical dimension control optimization methodology on shallow trench isolation substrate for sub-0.25 μm technology gate patterning Plasma etch-back planarization coupled to chemical mechanical polishing for sub 0.18 μm shallow trench isolation technologyThe resultant surface microscratches due to chemical mechanical polishing ͑CMP͒ can cause device failure and reduce production yield in the shallow trench isolation ͑STI͒ process. By using a plasma etch process to replace the overpolish step of CMP planarization (CMPϩplasma etch͒, we have reduced 10% of the total defect counts in the 0.15 m STI process. The CMP microscratches have been effectively smoothened by the additional plasma etch process. The electrical properties of the devices made via the CMP and the CMPϩplasma etch processes have been examined and compared. The off-state currents are similar. A higher breakdown voltage is found for the CMP ϩplasma etch process and can be interpreted by the local electrical-field concentration. Although the n ϩ / p and p ϩ /n junctions fabricated by the CMPϩplasma etch processes exhibit slightly larger leakage currents for certain test patterns, due to plasma damage, the products still meet the inline production requirements, and show promising results for yield improvement.

Analysis of Scratches Formed on Oxide Surface during Chemical Mechanical Planarization

“…Others also observed similar shapes of scratches on the oxide surface when polished with either the silica slurry or the ceria slurry. 3,5,12 It was proposed that the chatter mark shape ͑eyebrow shape͒ might be due to the presence of abnormally large size abrasives in the incoming slurry or because of the agglomeration of the slurry particles by the heat produced during the process. 12 Also, Lee et al claimed that the scratches formed by the ceria slurry might be due to the presence of a higher portion of large particles with a size of over 1.0 m in the slurry.…”

“…9 The scratches formed during the STI CMP process would create the problem during gate oxide integrity in semiconductor production. 3,5 Much research has been done on studying the methods of scratch reduction by controlling different polishing conditions and consumable parts, [3][4][5][6]9,10 but understanding the origins of the scratches generated on pattern wafers during real-time polishing has not been discussed. In a CMP process, consumable parts, such as a slurry, a polishing pad, and a diamond conditioning disk, can cause surface scratches.…”

“…During both processes, chemical mechanical planarization ͑CMP͒ is a key technology to planarize the oxide surface. [1][2][3][4][5] Various defects, such as organic residues, surface particles, dishing, erosion, and scratches, would be produced during the CMP process, but the most detrimental defect would be scratch formation. 6,7 The other types of defects produced could be removed by other means during post-CMP cleaning, but the removal of a scratch is not an easy task.…”