In this work, evidence of copper diffusion paths is shown with fine scanning electron microscopy failure analysis after electromigration failures in single damascene interconnect structures. For the polycrystalline grain structures, it is established that grain-boundary diffusion occurred, although experimental electromigration activation energy values are ranging from 0.65 to 0.80 eV. Narrow lines with quasibamboo microstructures showed interface diffusion located at upper surface of Cu damascene e.g., SiN capping layer interface, with activation energy values ranging from 0.80 to 1.06 eV. Due to the compression stress state in copper under electromigration and oxide cracking, respectively, SiN cap debonding occurred at the upper corners of the damascene trench and resulted in copper extrusions. For both microstructures, this failure mode provided decreased extrapolated lifetimes. Electromigration experiments on two-level damascene test structures provided an upper limit of Blech length threshold product jLth<4000 A/cm. Our data are finally compared to available literature results and to studies on AlCu.
Given the much discussed challenges of interconnect scaling at the 65-nm node, the choice of process architecture is a key determinant of performance and extendibility. An altemate trench-first with hardmask integration is described in this work, including subsequent benefits. BEOL design rules are detailed for the 65-nm architecture, supporting both "low-k and "ultra-low-k" backends, satisfying RC scaling requirements. Electrical parametric performance and yield are presented for a fully-integrated 300mm backend utilizing 65-nm design rules demonstrating the viability of this architecture for the 65-nm node and beyond.
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