We investigated the structure of in-grown stacking faults in the 4H–SiC(0001) epilayers. The in-grown stacking faults nucleate near the substrate/epilayer interface and expand the area with increasing epilayer thickness in a triangular shape. From transmission electron microscope observation, the formation of 1c of 8H polytype was confirmed in the in-grown stacking fault area. We also investigated the dependence of in-grown stacking fault density on the epitaxial growth rate, growth temperature, and substrate surface preparation.
Correlations between the free carrier lifetime of thick, lightly-doped n-type 4H-SiC epilayers and some deep levels (the Z 1/2 center, the EH 6/7 center and the D 1 center) were investigated. Concentrations of the Z 1/2 center and the EH 6/7 center correlated with the measured carrier lifetime to some extent. We have also compared the free carrier lifetime measured by time-resolved photoluminescence (TRPL) measurement and microwave-detected photoconductive decay (µ-PCD) measurement. The carrier lifetime measured by both technique was in close agreement. The carrier lifetime measured by LTPL increased at an elevated temperature of 500 K.
We investigated the structure of the in-grown stacking faults (SFs) in the 4H-SiC epilayers. The in-grown SFs exhibited the photoluminescence (PL) peaks representing phonon replicas with bandgap of 2.710 eV. The in-grown SFs were confirmed to be triangular-shaped by PL mapping and KOH etch pit observation. High-resolution TEM image showed that the in-grown SFs have an identical stacking sequence that differ from single or double Shockley SF. In addition, the density of the in-grown SF depended on growth conditions.
Growth of thick 4H-SiC layers was performed on ( 0001) and (000-1) substrates off-cut towards <11-20> or <1-100>. The roughness of the epilayers grown on the four different substrates was almost the same level, at 0.20-0.23 nm, while the epilayers grown on (000-1) exhibited particular large epi-defects with densities 10 -1 -10 1 cm -2 depending on the growth conditions. In both ( 0001) and (000-1), basal plane dislocations (BDs) inclined towards <1-100> with a tilt in the epilayer grown on substrates off-cut towards <1-100>, while the BDs lie along <11-20> for substrates off-cut towards <11-20>. No significant difference in densities of BDs and in-grown stacking faults for the different off-directions was revealed for (0001). For both ( 0001) and (000-1), the carrier lifetime of 4H-SiC epilayers was comparable for the different off-cut directions.
We fabricated epi pn diodes and investigated the correlation between defects included in the 4H-SiC epilayers and the leakage current of the pn diodes. Threading edge dislocations, screw dislocations, basal plane dislocations and in-grown stacking faults existed in the epilayers. From EL images of the diodes under reverse bias voltage, it was found that a line of edge dislocations forming a grain boundary and some screw dislocations caused an increase in leakage current. We also mention the influence of dissociated micropipes.
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