Structural analysis and reduction of in-grown stacking faults in 4H–SiC epilayers

Izumi, Syunsuke; Tsuchida, Hidekazu; Kamata, Isaho; Tawara, Takehiko

doi:10.1063/1.1927274

Cited by 116 publications

(152 citation statements)

References 5 publications

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“…To reduce IGSF densities at low or high C/Si ratios, elevation of growth temperature is helpful 42 since this will increase desorption of surface species. However a higher growth temperature may also reduce the growth rate and increase the surface roughness due to severe step bunching.…”

Section: Resultsmentioning

confidence: 99%

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Study of Surface Morphology, Impurity Incorporation and Defect Generation during Homoepitaxial Growth of 4H-SiC Using Dichlorosilane

Song

Chandrashekhar

Sudarshan

2014

ECS J. Solid State Sci. Technol.

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The growth of 4 • off-axis 4H-SiC epilayers by chemical vapor deposition is studied using dichlorosilane as the Si precursor in a chimney reactor. The unintentional and intentional nitrogen doping at various C/Si ratios and N 2 flow rates are investigated. The C/Si ratio has a significant influence on the growth rate, surface morphology, conversion of basal plane dislocations (BPDs), and generation of other defects (e.g., in-growth stacking faults and morphological defects). Addition of N 2 has no obvious influence on growth rate and BPD conversion. It is preferable to grow high quality n + epilayers at a C/Si ratio in the range of 1.3-1.8 along with the addition of a suitable amount of N 2 in consideration of high growth rate, good surface morphology, and low defect density. In this case, the conversion ratio of BPDs to threading edge dislocations is greater than 99.8% regardless of N 2 addition. Therefore >99.8% substrate BPDs can be buried in an n + buffer layer, which is beneficial to SiC bipolar power devices. No special treatment prior to, during or after the epigrowth is necessary. The epilayers with doping concentration all the way from p − (∼1e15 cm −3 ) to semi-insulating, then to n + (∼1e18 cm −3 ), can be achieved, giving a great range of flexibility in growth using dichlorosilane precursor. Further optimization of in-situ etching and growth conditions to eliminate step bunching has also been suggested. 4H-silicon carbide (4H-SiC) is a promising wide bandgap material for high power electronic devices, owing to its unique thermal and electrical properties such as high breakdown field, high thermal conductivity, and high electron saturation velocity.1,2 Chemical vapor deposition (CVD) is a well-developed technique adopted in semiconductor industry to produce high purity and high quality thin films.3 Homoepitaxial growth of SiC via the CVD technique is one of the key steps in the fabrication of high performance SiC devices. Currently, chloride-based CVD has attracted much interest to potentially replace the traditional silane based CVD for SiC epitaxial growth to reduce the Si droplet formation at high growth rates, because of the higher bonding energy of Si-Cl (400 kJ/mol) than SiSi (226 kJ/mol).4 Dichlorosilane (SiH 2 Cl 2 , DCS) is a gas (boiling point: 8.2• C) at room temperature. It has been demonstrated that using DCS and propane (C 3 H 8 ) as the precursors, high crystalline quality 8• off-axis SiC epilayers were achieved at a high growth rate (up to 100 μm/h). 5,6 At present, the standard off-axis angle of commercially available SiC substrates is lowered to 4• to reduce the material loss during substrate preparation from the crystal boules.Step-bunching is a typical surface feature of the epilayers grown on 4• off-axis substrates, resulting in increase in surface roughness. 7Morphological defects, specifically the triangular defects and inverted pyramids, are prone to be generated in epigrowth on low off-axis angle substrates. 8 Hence, determination of optimized growth conditions to produce SiC ...

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Section: Resultsmentioning

confidence: 99%

“…However a higher growth temperature may also reduce the growth rate and increase the surface roughness due to severe step bunching. 43 Providing a clean growth environment, 44 reducing the initial growth rate, 40 and/or optimization of surface pretreatment 42 may also help to reduce IGSF density.…”

Section: Resultsmentioning

confidence: 99%

Study of Surface Morphology, Impurity Incorporation and Defect Generation during Homoepitaxial Growth of 4H-SiC Using Dichlorosilane

Song

Chandrashekhar

Sudarshan

2014

ECS J. Solid State Sci. Technol.

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“…Step (4,4) for the 8H-stacking fault, (5, 3) for the (3, 5) type and (6, 2) for the double Shockley stacking fault, respectively [5][6][7]. Figure 6 shows the peak wavelength of the PL emission of the stacking fault area at RT of the Frank-and Shockley-type stacking faults with the stacking notations and schematics.…”

Section: Resultsmentioning

confidence: 99%

Photoluminescence Imaging and Wavelength Analysis of Basal Plane Frank-Type Defects in 4H-SiC Epilayers

Kamata

Zhang

Tsuchida

2012

MSF

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Abstract. Frank-type defects on a basal plane have been investigated using photoluminescence (PL) imaging microscopy and wavelength profile measurement. A wide range of emission in wavelength (>650nm) was observed from a Frank partial dislocation at the edge of the defect, while a narrow emission at around the visible light range was obtained from a stacking fault region. The emissions from a stacking fault region of three kinds of basal plane Frank-type defects were confirmed to have different wavelengths depending on their stacking structures.

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“…(6) Figure 4 shows PL spectroscopy assessment for luminescence at a wavelength of 750 nm or above. No luminescence originating from defects is observed in the section detected by X-ray topography.…”

Section: Assessment By Pl Spectroscopymentioning

confidence: 99%

Assessment of Stacking Faults in Silicon Carbide Crystals

2013

Sensors and Materials

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Key words: silicon carbide (SiC), staking fault, X-ray topography, photoluminescence (PL), mirror electron microscopy (MEM), atomic force microscopy (AFM) X-ray topography, photoluminescence (PL) spectroscopy, mirror electron microscopy (MEM), and atomic force microscopy (AFM) were employed to evaluate stacking faults in silicon carbide (SiC) crystals. The results reveal that transmission X-ray topography can be used to assess internal stacking faults in crystals, while PL spectroscopy and MEM can be used to assess stacking faults near the surface. The stacking faults assessed by these different methods were found to be the same. AFM revealed that sites where stacking faults were exposed on the surface had microscopic level differences of about 0.1 nm, which are thought to be generated by different etch rates during mirror polishing.

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Structural analysis and reduction of in-grown stacking faults in 4H–SiC epilayers

Cited by 116 publications

References 5 publications

Study of Surface Morphology, Impurity Incorporation and Defect Generation during Homoepitaxial Growth of 4H-SiC Using Dichlorosilane

Study of Surface Morphology, Impurity Incorporation and Defect Generation during Homoepitaxial Growth of 4H-SiC Using Dichlorosilane

Photoluminescence Imaging and Wavelength Analysis of Basal Plane Frank-Type Defects in 4H-SiC Epilayers

Assessment of Stacking Faults in Silicon Carbide Crystals

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