A novel architecture of a pipelined redundant-signed-digit analog to digital converter (RSD-ADC) is presented featuring a high signal to noise ratio (SNR), spurious free dynamic range (SFDR) and signal to noise plus distortion (SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC (residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.
The development and designing of advanced pipelined analog to digital converter (ADC) is becoming sophisticated day by day as dimensions and supply voltages used for devices are reducing. As the nanometer technology aids fabricating circuits with small footprints, we require high-performance Pipelined ADCs, which are able to rectify analog circuit non-idealities with digital calibration circuits. Digital background calibration is the most favorable solution instead of making changes in analog components in the deep submicron processes. This paper discusses some of the techniques for digital calibration that have been accepted to realize advanced pipelined ADCs. It was observed that on an average, for every two years, the efficiency of ADCs is enhanced by a factor of two. With constant technology scaling supply voltages have reduced and the devices operate at high speed. A closer inspection on SNDR, SFDR, INL and DNL of pipelined ADCs with different calibration techniques is presented here. Finally, a comparison on various design approaches is made to make a view towards additional enhancement in speed, power efficiency and functioning of ADCs.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.