On Calibration Techniques for Pipelined ADCs

Abstract

The development and designing of advanced pipelined analog to digital converter (ADC) is becoming sophisticated day by day as dimensions and supply voltages used for devices are reducing. As the nanometer technology aids fabricating circuits with small footprints, we require high-performance Pipelined ADCs, which are able to rectify analog circuit non-idealities with digital calibration circuits. Digital background calibration is the most favorable solution instead of making changes in analog components in the deep submicron processes. This paper discusses some of the techniques for digital calibration that have been accepted to realize advanced pipelined ADCs. It was observed that on an average, for every two years, the efficiency of ADCs is enhanced by a factor of two. With constant technology scaling supply voltages have reduced and the devices operate at high speed. A closer inspection on SNDR, SFDR, INL and DNL of pipelined ADCs with different calibration techniques is presented here. Finally, a comparison on various design approaches is made to make a view towards additional enhancement in speed, power efficiency and functioning of ADCs.