This paper analyses the effects of single-event transients (SETs) on CMOS low noise amplifiers (LNA) designed for a 0.18 mm technology. Two well-known topologies, the common-source and common-gate cascodes, have been analysed when heavy ions strike the most sensitive nodes of these structures. In order to simulate these strikes both a physics-based technology computer aided design (TCAD) tool and an electrical circuit domain simulator have been used. This way the physics information given by the TCAD tool is combined with the fast transient simulations performed in circuit simulators. To study their SET performance, the maximum voltage peak and the recovery time of the output signal were calculated for both LNAs. Additionally, a safe operating area can be defined, setting the boundaries for acceptable SETs. Radiation hardening by design techniques have been applied at the most vulnerable nodes of both LNAs. The proposed mitigation approaches make both LNAs hardened against radiation, considerably improving their SET performance.
This paper presents a thorough study of radiation effects on a frequency synthesizer designed in a 0.18 μ m CMOS technology. In CMOS devices, the effect of a high energy particle impact can be modeled by a current pulse connected to the drain of the transistors. The effects of SET (single event transient) and SEU (single event upset) were analyzed connecting current pulses to the drains of all the transistors and analyzing the amplitude variations and phase shifts obtained at the output nodes. Following this procedure, the most sensitive circuits were detected. This paper proposes a combination of radiation hardening-by-design techniques (RHBD) such as resistor–capacitor (RC) filtering or local circuit-redundancy to mitigate the effects of radiation. The proposed modifications make the frequency synthesizer more robust against radiation.
The development of wake-up receivers (WuR) has recently received a lot of interest from both academia and industry researchers, primarily because of their major impact on the improvement of the performance of wireless sensor networks (WSNs). In this paper, we present the development of three different radiofrequency envelope detection (RFED) based WuRs operating at the 868 MHz industrial, scientific and medical (ISM) band. These circuits can find application in densely populated WSNs, which are fundamental components of Internet-of-Things (IoT) or Internet-of-Everything (IoE) applications. The aim of this work is to provide circuits with high integrability and a low cost-per-node, so as to facilitate the implementation of sensor nodes in low-cost IoT applications. In order to demonstrate the feasibility of implementing a WuR with commercially available off-chip components, the design of an RFED WuR in a PCB mount is presented. The circuit is validated in a real scenario by testing the WuR in a system with a pattern recognizer (AS3933), an MCU (MSP430G2553 from TI), a transceiver (CC1101 from TI) and a T/R switch (ADG918). The WuR has no active components and features a sensitivity of about −50 dBm, with a total size of 22.5 × 51.8 mm2. To facilitate the integration of the WuR in compact systems and low-cost applications, two designs in a commercial UMC 65 nm CMOS process are also explored. Firstly, an RFED WuR with integrated transformer providing a passive voltage gain of 18 dB is demonstrated. The circuit achieves a sensitivity as low as −62 dBm and a power consumption of only 528 nW, with a total area of 634 × 391 μm2. Secondly, so as to reduce the area of the circuit, a design of a tuned-RF WuR with integrated current-reuse active inductor is presented. In this case, the WuR features a sensitivity of −55 dBm with a power consumption of 43.5 μW and a total area of 272 × 464 μm2, obtaining a significant area reduction at the expense of higher power consumption. The alternatives presented show a very low die footprint with a performance in line with most of the state-of-the-art contributions, making the topologies attractive in scenarios where high integrability and low cost-per-node are necessary.
This paper presents a low power 2.4 GHz receiver front-end for 2.4-GHz-band IEEE 802.15.4 standard in 0.18 µm CMOS technology. This receiver adopts a low-IF architecture and comprises a variable gain single-ended low-noise amplifier (LNA), a quadrature passive mixer, a variable gain transimpedance amplifier (TIA) and a complex filter for image rejection. The receiver front-end achieves 42 dB voltage conversion gain, 10.3 dB noise figure (NF), 28 dBc image rejection and -5 dBm input third-order intercept point (IIP3). It only consumes 5.5 mW. Index terms: RF front end, CMOS RFIC, IEEE 802.15.4 receiver, low-noise amplifier (LNA), passive quadrature mixer, complex filter.
In this work, the design and implementation of an open source software and hardware system for Internet of Things (IoT) applications is presented. This system permits the remote monitoring of supplied data from sensors and webcams and the control of different devices such as actuators, servomotors and LEDs. The parameters which have been monitored are brightness, temperature and relative humidity all of which constitute possible environmental factors. The control and monitoring of the installation is realised through a server which is managed by an administrator. The device which rules the installation is a Raspberry Pi, a small and powerful micro-computer in a single board with low consumption, low cost and reconfigurability.
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