The ASIC for multi-speaker speech recognition is design in this paper. The LPCderived cepstral coefficients are chosen as speech features. Templates are trained by K---means clustering algorithm. Two stage recognition system can not only improve recognition accuracy, but also reduce the delay. The first stage of recognition system uses speech spectrum dif€ereme(SSD) algorithm. The second stage uses DTW. The whole recognition system is design into ASIC on high level with VHDL and simulated in Powerview.
A test point selection algorithm TEPSAUS (TEst-Point Selection Algorithm Using Small signal model) for scan based build-in self-test (BIST) is proposed in this paper. In order to reduce the computational complexity, the algorithm uses Small Signal Model (SSM) to build recursion formulas for cost reduction functions. With the recursion functions, the cost reduction functions can be calculated efficiently.
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