Chip embedded technology enables advanced integration of modern electronic package structures due to its characteristics of small size, higher performance, lower overall cost and reduction of time to market. Moreover, stacking multiple layers of embedded components can allow an even higher capacity of devices and packaging density. Comparing to 3D interconnection by through silicon via (TSV), device embedded module can have relevant effects by using PCB compatible process though the size and transmitting path is slightly higher than 3D IC modules. However, warpage issue is one of the significant factors that affect the manufacturing of device embedded products due to the asymmetric package form. A strong and robust substrate or core layer, such as high Tg FR4 substrate, BT substrate or Cu lead frame, is often required to provide a stiffening effect for the structure to prevent from severe warpage. In order to acquire even thinner package form, finer L/S specifications, and higher density of interconnection, coreless substrate may be one of the solution to meet the demand. But the asymmetric characteristic of embedded package structure may be regarded as a challenge when applied in coreless structure without a core layer. In this paper, a new type dielectric material with the characteristic of low CTE is disclosed. When it was applied in an asymmetric package structure with embedding chip, warpage behavior was found suppressed comparing to conventional dielectric materials. Moreover, when it was applied in a coreless structure with chip embedded, the structure can still maintain considerable flatness. The process feasibility of laser via forming, Cu plating was evaluated, while tensile strength of the plated Cu and reliability of the laminated structure were examined. An additional PI material was coated as the release layer in the forming of the coreless structure. The concept of asymmetric built-up coreless structure was brought up according to the materials' characteristics and regarded as a potential solution for 3D System-in-Package in this study.
In this research, thousands of 20 µm pitch microbumps with a diameter of 10 µm and a structure of pure Sn cap on Cu pillar were electroplated on 8 inch wafers, and those wafers were then respectively singularized to be top chip (5 mm × 5 mm) and bottom Si interposer (10 mm × 10 mm) for stacking. Two methods including conventional reflow and solid-liquid interdiffusion (SLID) bonding were chosen to interconnect the microbumps on the chip and on the interposer. In the former case, the as-plated Sn caps were fluxed with Senju Metal's WF-6400 paste, and the chip was then placed on a Si interposer using a SÜSS FC-150 bonder at room temperature. Afterwards, the Sn caps on the chip and on the Si interposer were melted and interconnected at a peak temperature of 250ºC in an ERSA's reflow oven (Hotflow 7). The flux residues were cleaned after reflow, and the microgap between the chip and the Si interposer were fully sealed by a Namics' capillary underfill with an average filler size of 0.3 um. Regarding the SLID bonding, the oxides on the as-plated Sn caps were removed by a plasma etcher first, and then the chip was placed on the interposer by the SÜSS FC-150 bonder as well, subsequently, the Sn caps were heated up to 260ºC to react with Cu to form Cu 6 Sn 5 completely. In the final, the intermetallic microjoints were also protected by the same capillary underfill. After assembling, the JEDEC preconditioning test was used to screen the test vehicles for reliability assessment, and then a temperature cycling test was performed to predict the lifespan of the microjoints. The test results showed that the microjoints formed by SLID bonding provided a superior reliability performance to those assembled by reflow. According to the images of focus ion beam (FIB), the intermetallic phases of Cu 6 Sn 5 and Cu 3 Sn coexisted at the interface between the Sn cap and the Cu pillar after reflow once, and some Kirkendall voids were found at the Cu 3 Sn / Cu pillar interface concurrently. When the microjoints undergone 3 times more reflow in the preconditioning test, the Kirkendall voids accumulated and was going to speed up the failure of microjoints as experienced just hundreds of temperature cycles. On the other hand, the microjoints produced by SLID bonding have not failed when thousands of temperature cycles passed. Based on those evidences, it is claimed here that SLID is an efficient bonding method to form reliable intermetallic microjoints for chip stacking.
Flip chip package has been reported to be an ideal package solution of high bandwidth devices because of a lower power loss and a short transmission route of signal. However, some failure modes such as solder joint crack, delamination of substrate or low-k delamination within IC were often found after reliability verification. One of the key factors of failure is attributed to the mismatch of CTE values between Si chip (4 ppm) and substrate (tens ppm), and ultralow CTE laminate materials are really needed to improve the reliability to automotive-level. In this study, a 1/2/1 substrate with a dimension of 12 mm 12 mm 0.22 mm was made by laminating low-CTE or low-Young's modulus prepreg on a 100 m thick core. FCCSPs with four types of core and PP-like build-up material were assembled and tested to understand the effect of selected material properties on the reliability response. The simulation results revealed that the effects of selected material properties such as low CTE and low Young's modulus on the warpage behavior were not apparent. Also, the warpage of the tested FCCSPs might not be the dominated factor to affect the reliability performance. Simulate induced stress/strain during reliability test would be the major factor to decide the reliability performance of solder joints. The FCCSP having the highest maximum strain within the solder joints would fail after thermal cycling test. Low CTE material could reduce simulate maximum strain within the solder joints. In addition, the effect of low CTE seemed to be more prominent than that of low Young's modulus on simulate maximum strain value. By numerical analysis and reliability test, beneficial effect of prepreg with low-CTE and low Young's modulus on the reliability response had been confirmed.
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