Current organic substrates are limited to lines/space 10/10 μm and via size around 50 μm. However, the semiconductor with advance node needs fine line/space of 5/5 or 3/3 and even 2/2 μm in the future. Interposer provides a high density interconnection with fine line and small via that cannot be matched by current laminate substrate technology. We have proposed a new structure that embedded interposer to organic substrate (Flip chip -Embedded Interposer Carrier, FC-EIC ® ). This structure has virtues of know good substrate and compatible with current packaging and assembly infrastructure. We have demonstrated the feasibility of integrating silicon interposer to a laminate substrate.In this paper, we evaluated the feasibility of integration of a glass interposer into an organic substrate. The selection of glass, temporary bonding materials and built-up dielectric materials were established. The compatibility of lamination and built-up process with glass interposer was demonstrated. By using dielectric materials with small CTE and high modules together with an innovative structure, significant warpage reduction of the EIC-glass was achieved. For a 10 cm x 10 cm laminated carrier with a proper dielectric material set, the panel warpage of the EIC-glass structure can be reduced from 20 mm to less than 3 mm. The EIC-glass structure has been tested under 500 TCT cycles and no glass damage and delamination between glass and the built-up dielectric film was observed.
IntroductionSemiconductor technology is rapidly moving from 28 nm to 20 nm and even to 16 nm nodes. However the organic substrate, which is widely used as a substrate for silicon chips, is difficult to match the line shrinking speed of the semiconductor. Current organic substrate can support circuit pattern of line/space of 10/10 μm, but the industry is looking for line/space of 5/5 μm and even in some case 2/2 μm in the future. The material and tools to support this fine line in organic substrate is under intense development in the industry.But for semiconductor industry, the infrastructure of fine lines and small vias are already there. 2.5D and 3D packaging integration using semiconductor technology and silicon are under intense development. Silicon interposer can meet fine line/space requirement easily by means of wafer level processes. However, the cost of processing is very high. This prevents the wide use of silicon interposer. We have proposed a new FC-EIC ® structure which embedded the interposer to an organic substrate in ECTC 2013 [1]. The EIC structure has lower profile and possible better electrical performance by eliminating the solder joints between the interposer and the organic substrate. The integration of silicon interposer and