In this study, the authors investigated atomic layer deposition (ALD) of B2O3 and BN for conformal, ultrashallow B doping applications and compared the effect of dopant-containing overlayers on sheet resistance (Rs) and B profiles for both types of films subjected to a drive-in thermal anneal. For the deposition of B2O3, tris(dimethylamido)borane and O3 were used as coreactants and for the deposition of BN, BCl3 and NH3 were used as coreactants. Due to the extreme air instability of B2O3 films, physical analysis was performed on B2O3 films, which were capped in-situ with ∼30 Å ALD grown Al2O3 layers. For the BN films, in-situ ALD grown Si3N4 capping layers (∼30 Å) were used for comparison. From spectroscopic ellipsometry, a thickness decrease was observed after 1000 °C, 30 s anneal for the B2O3 containing stack with 60 ALD cycles of B2O3, whereas the BN containing stacks showed negligible thickness decrease after the annealing step, regardless of the number of BN cycles tested. The postanneal reduction in film thickness as well as decrease in Rs for the B2O3 containing stack suggests that the solid state diffusion dopant mechanism is effective, whereas for the BN containing stacks this phenomenon seems to be suppressed. Further clarification of the effectiveness of the B2O3 containing layer compared to the film stacks with BN was evidenced in backside secondary ion mass spectrometry profiling of B atoms. Thus, B2O3 formed by an ALD process and subsequently capped in-situ followed by a drive-in anneal offers promise as a dopant source for ultrashallow doping, whereas the same method using BN seems ineffective. An integrated approach for B2O3 deposition and annealing on a clustered tool also demonstrated controllable Rs reduction without the use of a capping layer.

This work investigates the application of slot plane antenna plasma oxidation (SPAO) during dielectric depositionto processTiN/AlO/ZrO2/Ge MOS capacitors. The impact of SPAO exposure on effective oxide thickness (EOT), leakage current, interface state density (D it), C-V hysteresis, oxide breakdown characteristics have been studied. Considerable degradation of electrical properties has been observed with SPAO being performed before AlO/ZrO2 gate stack deposition. When SPAO is performed in between AlO/ZrO2deposition, moderate increase in EOT and significant decrease in D it was observed, which can be attributed to the formation of a thicker GeOX layer. On the other hand, when SPAO is performed after the deposition of both the high-k layers, higher D it was observed suggesting that a thinner GeOX layer formation. Time zero dielectric breakdown (TZDB) characteristics indicate that plasma exposure after and in between AlO/ZrO2 deposition enhances the dielectric quality by film densification due to plasma exposure. It was demonstrated that improved dielectric and interface quality can be achieved when ALD-AlO/ZrO2 gate stacks were exposed to SPAO.

In this paper, the multilevel switching behaviors of resistive random-access memory (RRAM) devices with three different dielectric materials such as HfO2, HfZrO2 and HfAlO2 are investigated. We have further explored the switching characteristics with two different top electrode materials and with different processing environments. In all devices we have introduced a thin buffer layer to reduce switching power and improve the uniformity. Variation in the resistive behavior (Roff/Ron values) of different RRAM structures were observed and was correlated with possible oxygen vacancy related defects present in the dielectric.

RC-time delay in Cu interconnects is becoming a significant factor requiring further performance improvements in future nanoelectronic devices. Choice of alternate interconnect materials, as for example, refractory metals, and subsequent integration with underlying barrier and liner layers are extremely challenging for the sub-10 nm nodes. The development of conformal deposition processes for alternate interconnects, liner, and barrier materials are crucial in order for implementation of a possible replacement for Cu interconnects for narrow line widths. In this study we report on ultra-thin (~ 3nm) chemical 2 vapor deposition (CVD) grown ruthenium films on 0.5 and 1 nm thick metal nitride (TiN, TaN) barrier layers deposited via atomic layer deposition (ALD). Using scanning electron microscopy, we determined the effect of the underlying barrier layer on the coverage of the ruthenium overlayer. We utilized synchrotron x-ray diffraction with in-situ rapid thermal annealing to investigate the thermal stability of the barrier layers and determine the effective activation energies of barrier failure leading to ruthenium monosilicide formation.For Ru films deposited directly on Si and on 0.5 nm MN (M=Ti, Ta) covered Si substrates, silicide formation proceeds via a two-step crystallization process involving lateral nucleation above ~ 440 °C followed by thickening of the ruthenium monosilicide layer above ~520 °C. This silicidation temperature of ~ 440 °C could be potentially problematic in back-end-of-the-line (BEOL) processing since it is close to the typical thermal budget used. However ~1 nm thick ALD MN (M=Ti, Ta) was found to be adequate to block silicide formation up to ~ 580 °C and ~ 620 °C for TiN and TaN, respectively, and also aided in superior coverage of the CVD ruthenium overlayer (>90%). The results reported here might be useful to ascertain annealing temperature and time for BEOL process and integration optimization without reaching a state where ruthenium silicides start forming.

This paper presents studies performed in engineering high-κ metal gate stacks by using capping layers containing Group IIA and IIIB elements. Both high-κ gate dielectric (HfO 2 ) and capping materials, namely, the oxides of barium, lanthanum and yttrium are deposited by atomic layer deposition (ALD) to offer superior process control and flexibility. Position specific insertion of cap layers into the gate stack is studied and the device tradeoffs are highlighted. The magnitude of threshold voltage shift is correlated to the electronegativity of the cap layer species and its relative position in the gate stack. For a given cap position, BaO provides the maximum threshold voltage shift with the highest penalty in carrier mobility, followed by La 2 O 3 and Y 2 O 3 caps. Both lanthanum and barium incorporation into the high-κ gate stack provides a T inv scaling benefit. Ozone based ALD processes are shown to adversely impact T inv scaling due to the re-growth of the interface layer between the high-κ and the silicon substrate. This penalty is exacerbated in gate stacks with cap layers situated directly below the high-κ film. Significant improvements in T inv scaling are obtained by migrating to a water based ALD process.