Balsa provides a rapid development flow, where asynchronous circuits are created from high-level specifications, but the syntax-driven translation used by the Balsa compiler often results in performance overhead. To reduce this performance penalty, various control resynthesis and peephole optimization techniques are used; in this paper, STG-based resynthesis is considered. For this, we have translated the control parts of almost all components used by the Balsa compiler into STGs; in particular we separated the control path and the data path in the data components. A Balsa specification corresponds to the parallel composition of such STGs, but this composition must be reduced. We have developed new reduction operations and, using real-life examples, studied various strategies how to apply them. This research was supported by DFG-project 'Optacon' VO 615/10-1 and WO 814/3-1.This report is the full version of the extended abstract [1].
The paper presents the design of a generalised asynchronous arbiter with a two-stage architecture that efficiently handles requests from multiple concurrent channels. The first stage of the arbiter monitors the incoming requests and locks their state as soon as one or more requests are detected. The second stage performs arbitration based on the locked state of the requests and produces the corresponding grant signals.The separation of the two stages is crucial for reducing the complexity of the arbitration logic, which allows us to obtain practical implementations for complex arbitration protocols.Several application examples of the generalised arbiter are proposed and evaluated in terms of scalability with respect to the growing number of request channels. The presented designs are verified to have no hazards or deadlocks using methods based on circuit Petri nets.
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