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We demonstrate electrically functional 0.099μm 2 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) highk/metal gate FinFETs with L g~4 0nm, 12-17nm wide Fins, and cell β ratio~1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ≥30nm-wide contacts. SRAM cell with SNM>10%V DD down to 0.4V, and healthy electrical characteristics for the cell transistors [SS~80mV/dec, DIBL~50-80mV/V, and V Tlin ≤0.2V (PMOS), V Tlin~0 .36V (NMOS)] are reported.

We report on a major advancement in full-field EUV Lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186µm 2 6T-SRAMs, with W-filled contacts. Alignment to other 193nm immersion litho levels shows very good overlay values ≤20nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3σ≤7nm after double-dipole 193nm immersion litho (NA=0.85) and 3σ≤9nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM V DD scalability down to 0.6V (SNM>0.1V DD ) and healthy electrical characteristics (V T , σ(∆V T ), I-V) for the cell transistors are obtained.

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