This work presents a unique time-efficient and reliable floorplan algorithm DOTFloor (Diffusion Oriented Time-improved Floorplanner), built around a SA (Simulated Annealing) engine and targeted to optimize the peak on-chip temperature along with the traditional design metrics like chip area and wire length. This paper also proposes a novel heat-diffusion based stochastic thermal model called the FATT (Fast Assumption Technique for Temperature) which provides a fast assumption of the degree of hotness during the optimization process. The incorporation of FATT in DOTFloor results in a significant improvement in the run time of the optimization process. Upon experimentation on MCNC (Microelectronics Center of North Carolina) benchmark circuits with the proposed floorplanner, a good optimization in area, wire length metric and peak on-chip temperature with a significant reduction in execution time have been achieved over the existing floorplanning tool, the HotFloorplan.
Since hotspots and temperature gradients are reliability and performance-critical issues in processors, thermal awareness finds a vital place in the processor design cycle. Incorporating thermal awareness at the level of physical design, this work proposes a new, fast, and efficient thermal aware placement algorithm called the Thermal Aware Matrix Placement Optimizer (TAMPO) for gate arrays. The algorithm TAMPO is composed of the following components: an improved heat diffusion aware cell arrangement technique called the Initial Matrix Generator (IMaGe), a unique stochastic thermal model based on a thermally improved interpretation of the well known Matrix Synthesis Problem (MSP) and a Simulated Annealing (SA) engine for finding the global optimum solution. TAMPO targets to reduce the peak temperature while maintaining improved values of temperature gradients and the standard deviation in cell temperature with respect to the average chip temperature. This work also presents a methodology, the Co-optimized TAMPO, which extends the concept of TAMPO to simultaneously optimize the thermal attributes and the wirelength of a chip. The proposed algorithms realize a placement in matrix arrangement and upon experimentation on the ISCAS89 benchmark circuits encouraging results have been obtained.
An important functional component of a processor is the Arithmetic Logic Unit (ALU). ALU's are at the core of a microprocessor where all mathematical and logical computations are being performed. ALU's are also one of the most power hungry sections in the processor's data path and are often the possible location of hot-spots. Efficient design of an ALU is therefore a critical issue in processor design environment. Conventional techniques of ALU design employ either tree or chain structure. The Tree structure is faster but requires larger area and hence suffers from more power dissipation. The Chain structure on the other hand requires lesser area, has comparatively lower power dissipation but is considerably slower. Therefore, their lies a huge scope for hybridizing both the ALU structures to obtain an intermediate hybrid ALU architecture which is efficient in Area, Speed and Power dissipation. In this paper, we have proposed a unique approach of hybrid customization based on Genetic Algorithm for the ALU design by mixing both the chain and tree structures to obtain a hybrid structure. A weighted cost function comprising of Delay, Area and Power dissipation parameters has been considered to find the best fit hybrid ALU architecture. Hybrid structure has shown an improvement of about 15.14% in terms of overall cost over the Tree structure and about 39.71% improvement over the chain structure when Delay, Power and Area were given a weightage of 25%, 25% and 50% respectively.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.