An elitist area-power density trade-off in VLSI floorplan using genetic algorithm

Das, Apangshu; Choudhury, Somnath Roy; Kumar, B. Kalyan; Pradhan, Sambhu Nath

doi:10.1109/icece.2012.6471654

Cited by 7 publications

(5 citation statements)

References 7 publications

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“…Elitism is a technique to prevent losing the best found solution in a population [14]. We copy best 20% chromosomes directly to the next generation and consider them as elite group.…”

Section: Elitismmentioning

confidence: 99%

Thermal aware output polarity selection of programmable logic arrays

Das

Pradhan

2015

2015 International Conference on Electronic Design, Computer Networks &Amp; Automated Verification (EDCAV)

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Intensive scaling and large number of logic blocks embedded within a VLSI chip results increased power-densities. Power-density directly converging into temperature which reduces the yield of the circuit. Adverse affect of power-density reduction is increase in area. So, there is a trade-offs between area and powerdensity. Previous works has been done on the polarity selection of outputs of programmable logic arrays (PLA) for its reduced area or low power realization. In this paper, we present a heuristic based on genetic algorithm to increase the sharing of product terms in multi-output PLA by selecting the proper output polarity and a suitable area and power-density trade-off has been enumerated. This is the first ever effort to incorporate the power-density in polarity selection process. The proposed algorithm has been validated with the LGSynth93 benchmark circuit. A comparative study of our approach is done with 'espresso' and 'espresso -Dopo' methodology. We obtained 17.53% (26.69%) improvement in area (power-density) with respect to 'espresso'. Also 7.87% in area and 27.95% in power-density with respect to 'espresso -Dopo' has been reported in this paper.

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“…Elitism is a technique to prevent losing the best found solution in a population [14]. We copy best 20% chromosomes directly to the next generation and consider them as elite group.…”

Section: Elitismmentioning

confidence: 99%

Thermal aware output polarity selection of programmable logic arrays

Das

Pradhan

2015

2015 International Conference on Electronic Design, Computer Networks &Amp; Automated Verification (EDCAV)

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“…Elitism is a technique to prevent the degradation of the quality of the next generation. This is done by transferring few best-fitted chromosomes from present generation to next generation [34]. This is done not to lose the best-found solutions in a population.…”

Section: Elitism (Direct Copy)mentioning

confidence: 99%

Area-Power-Temperature Aware AND-XOR Network Synthesis Based on Shared Mixed Polarity Reed-Muller Expansion

Das¹,

Pradhan²

2018

IJISA

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Modern Integrated circuits (ICs) suffer from excessive power and temperature issues because of embedding a large number of applications on small silicon real estate. Low power technique is introduced to reduce the power. With the reduction of power, area of circuit increases and vice versa. It shows a trade-off nature between them. Increase of area is against the trend of technology scaling which demands small area. Due to small area and high power dissipation, power-density increases. As power-density is directly converging into temperature, it emerges as a challenge in front of the VLSI design engineer to minimize the effect of temperature by reducing power-density. In this work, an attempt has been made to reduce the effect of powerdensity along with area and power so that AND-XOR based circuit is balanced in terms of area, power, and temperature. AND-XOR based reed-muller (RM) mixed polarity circuit forms are considered in this work. Polarity conversions are made in such a way that possibility of maximum sharing among the sub-function is increased. Genetic algorithm is (a non-exhaustive heuristic algorithm) used to select the polarity of the input variable for maximum sharing. The proposed synthesis approach shows 27.11%, 20.69%, and 32.30% savings in area, power, and power-density respectively than that of reported results. For the validation of the proposed approach, the best solutions are implemented in Cadence digital domain to obtain actual silicon area and power consumption. HotSpot tool is used to get the absolute temperature of the circuit.Spreader thickness = 1mm, Chip to spreader interface thickness = 0.020mm, Dynamic temperature management = above 85 °C .

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“…Elitism is a technique to prevent losing the best-found solution in a population [22]. The best 20% chromosomes of the present generation are directly copied to the next generation and these are considered as the "elite group."…”

Section: Elitism (Direct Copy)mentioning

confidence: 99%

Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

Das

Pradhan

2016

VLSI Design

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The increased number of complex functional units exerts high power-density within a very-large-scale integration (VLSI) chip which results in overheating. Power-densities directly converge into temperature which reduces the yield of the circuit. An adverse effect of power-density reduction is the increase in area. So, there is a trade-off between area and power-density. In this paper, we introduce a Shared Reed-Muller Decision Diagram (SRMDD) based on fixed polarity AND-XOR decomposition to represent multioutput Boolean functions. By recursively applying transformations and reductions, we obtained a compact SRMDD. A heuristic based on Genetic Algorithm (GA) increases the sharing of product terms by judicious choice of polarity of input variables in SRMDD expansion and a suitable area and power-density trade-off has been enumerated. This is the first effort ever to incorporate the power-density as a measure of temperature estimation in AND-XOR expansion process. The results of logic synthesis are incorporated with physical design in CADENCE digital synthesis tool to obtain the floor-plan silicon area and power profile. The proposed thermal-aware synthesis has been validated by obtaining absolute temperature of the synthesized circuits using HotSpot tool. We have experimented with 29 benchmark circuits. The minimized AND-XOR circuit realization shows average savings up to 15.23% improvement in silicon area and up to 17.02% improvement in temperature over the sum-of-product (SOP) based logic minimization.

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An elitist area-power density trade-off in VLSI floorplan using genetic algorithm

Cited by 7 publications

References 7 publications

Thermal aware output polarity selection of programmable logic arrays

Thermal aware output polarity selection of programmable logic arrays

Area-Power-Temperature Aware AND-XOR Network Synthesis Based on Shared Mixed Polarity Reed-Muller Expansion

Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

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