A genetic algorithm approach for hybrid ALU design

Abstract

An important functional component of a processor is the Arithmetic Logic Unit (ALU). ALU's are at the core of a microprocessor where all mathematical and logical computations are being performed. ALU's are also one of the most power hungry sections in the processor's data path and are often the possible location of hot-spots. Efficient design of an ALU is therefore a critical issue in processor design environment. Conventional techniques of ALU design employ either tree or chain structure. The Tree structure is faster but requires larger area and hence suffers from more power dissipation. The Chain structure on the other hand requires lesser area, has comparatively lower power dissipation but is considerably slower. Therefore, their lies a huge scope for hybridizing both the ALU structures to obtain an intermediate hybrid ALU architecture which is efficient in Area, Speed and Power dissipation. In this paper, we have proposed a unique approach of hybrid customization based on Genetic Algorithm for the ALU design by mixing both the chain and tree structures to obtain a hybrid structure. A weighted cost function comprising of Delay, Area and Power dissipation parameters has been considered to find the best fit hybrid ALU architecture. Hybrid structure has shown an improvement of about 15.14% in terms of overall cost over the Tree structure and about 39.71% improvement over the chain structure when Delay, Power and Area were given a weightage of 25%, 25% and 50% respectively.