In order to efficiently store, retrieve and process big data, the data-centric computing paradigm is adopted and an application-driven storage class memory (SCM)/NAND flash hybrid solid-state drive (SSD) is designed. SSD data management algorithms minimize data movement inside the storage system and the SSD system design parameter, SCM/NAND capacity ratio, is chosen depending on the application. Design guidelines are proposed, based on the evaluation of three SCM/NAND flash hybrid SSDs with: (1) write-back (WB) cache, (2) write-optimized data management (WO-DM) and (3) read-write balanced data management (RWB-DM) algorithms. The WO-DM algorithm achieves the highest SSD performance for write-intensive applications, whereas RWB-DM is most appropriate for read-hot (frequently accessed)-random workloads. As long as the workload is not read-cold-sequential or write-cold-sequential, adding SCM to the NAND SSD system is cost-effective to boost performance. Less than 10% SCM/NAND capacity ratios provides 10× speed, compared to the NAND flash-only SSD.

This paper proposes a mix-and-match design method for triple level cell (TLC)/multi level cell (MLC) NAND flash hybrid and exchangeable storage arrays. A TLC-NAND flash provides an low cost and high capacity memory solution. However the reliability and access latency of TLC NAND flash are degraded from MLC NAND flash. Additionally, the block unit write is preferable for TLC NAND flash since the write order is complicated due to narrow data margin and write disturbance. The proposed solution combines TLC and MLC NAND flash memories for a storage array. To reduce access to TLC NAND flash, the stored data is screened and only the static frozen data are stored into TLC NAND flash with a Round-Robin frozen data collection algorithm (RR-FDCA). Furthermore, the proposed chip exchanging method extends the solid-state drive (SSD) lifetime without system suspending. As a result, in spite of moderate characteristics of TLC NAND flash, the proposed storage array can achieve 29% write energy saving and 56% write performance enhancement with 17% cost reduction, compared with the conventional MLC-only SSD.

This paper proposes TLC/MLC NAND flash mix-and-match design method for exchangeable storage array. The proposed Round-Robin frozen data collection achieves 56% higher write performance and 29% write energy reduction compared with the conventional MLC only SSD. SSD card exchange method is also presented to realize sustainable and flexible storage arrays.

An intra-panel interface for large size and high refresh rate panel is proposed. A source synchronous clocking with a new calibration scheme enables data skew adjustment while eliminating sensitive analog circuits in source driver. 2Gbps operation required for a 80-inch 4K2K panel with the 8-bit RGB and 240Hz driving is verified.

An enterprise-grade SSD with TLC (3b/cell) NAND Flash is presented with three techniques that achieve high speed and high reliability. Quick low-density parity-check (LDPC) reduces the read latency of 1Xnm TLC NAND Flash SSD by 83%. Dynamic V TH optimization and auto data recovery reduce the NAND Flash bit-error rate (BER) by 80% and 18%, respectively. These techniques can be implemented in the SSD controller without circuit overhead. No modification is required to the TLC NAND flash.Enterprise storage demands fast speed and good reliability with high-density for big data applications. Though TLC NAND Flash SSD has the bit cost advantage over MLC (2b/cell) NAND Flash SSD, the adoption in the enterprise market is limited due to its poor speed and reliability. Real-time online analytical processing (OLAP) applications require a quick response from SSD. In real-world workloads, temporal data locality causes read requests to concentrate on the same memory cells. The frequently read data (hot data) suffers from the read disturb while cold data fail due to the data retention. To overcome performance and reliability problems of TLC NAND flash SSD, this paper describes three techniques shown in Fig. 7.7.1.To efficiently correct errors with a short latency, this paper presents quick LDPC. The read latency is 83% lower than advanced error-prediction LDPC (AEP-LDPC) error-correcting code (ECC) [1]. When memory cells wear-out and errors exceed the ECC capability, dynamic V TH optimization adaptively selects the optimal read reference voltage (V Ref ) and increases the V TH read margin. As a result, measured errors are reduced by 80%. Auto data recovery compensates the V TH decrease (the data retention error) with the V TH increase (the read disturb error).First, the LDPC is shown in Fig. 7.7.2. Figure 7.7.3 shows the total read latency and the measured reliability. In the enterprise MLC NAND Flash SSD, fast BCH ECC [2] is used. The error-correction capability of BCH is not sufficient for the enterprise use of TLC NAND Flash because enterprise storage requires higher endurance than consumer storage. The soft-decoding LDPC [3] corrects more errors than BCH ECC. However, it needs analog V TH to calculate the loglikelihood ratio (LLR) and 49-time V Ref sensing is necessary and the read latency increases to 2.3ms. V Ref sensing is defined as sensing a memory cell with one of the reference level. The conventional AEP-LDPC estimates LLR by the harddecision (digital) V TH , the write/erase (W/E) cycle, the retention time and intercell coupling information. Since the analog V TH is not used, the read latency decreases to 1ms. Yet, AEP-LDPC is still 7× slower than BCH ECC. In AEP-LDPC, 21-time V Ref sensing are required to read neighboring cell data in both wordline and bitline directions.To accelerate the read while securing the high reliability, the quick LDPC reads only one of upper/middle/lower pages, corresponding to 2 to 3V Ref sensing. The total read latency is 173μs, which is comparable with the latency of BCH ECC of 146μs. Th...