Background
Clinical observations have shown that there is a relationship between coronavirus disease 2019 (COVID-19) and atypical lymphocytes in the peripheral blood; however, knowledge about the time course of the changes in atypical lymphocytes and the association with the clinical course of COVID-19 is limited.
Objective
Our purposes were to investigate the dynamics of atypical lymphocytes in COVID-19 patients and to estimate their clinical significance for diagnosis and monitoring disease course.
Materials and methods
We retrospectively identified 98 inpatients in a general ward at Kashiwa Municipal Hospital from May 1st, 2020, to October 31st, 2020. We extracted data on patient demographics, symptoms, comorbidities, blood test results, radiographic findings, treatment after admission and clinical course. We compared clinical findings between patients with and without atypical lymphocytes, investigated the behavior of atypical lymphocytes throughout the clinical course of COVID-19, and determined the relationships among the development of pneumonia, the use of supplemental oxygen and the presence of atypical lymphocytes.
Results
Patients with atypical lymphocytes had a significantly higher prevalence of pneumonia (80.4% vs. 42.6%, p < 0.0001) and the use of supplemental oxygen (25.5% vs. 4.3%, p = 0.0042). The median time to the appearance of atypical lymphocytes after disease onset was eight days, and atypical lymphocytes were observed in 16/98 (16.3%) patients at the first visit. Atypical lymphocytes appeared after the confirmation of lung infiltrates in 31/41 (75.6%) patients. Of the 13 oxygen-treated patients with atypical lymphocytes, approximately two-thirds had a stable or improved clinical course after the appearance of atypical lymphocytes.
Conclusion
Atypical lymphocytes frequently appeared in the peripheral blood of COVID-19 patients one week after disease onset. Patients with atypical lymphocytes were more likely to have pneumonia and to need supplemental oxygen; however, two-thirds of them showed clinical improvement after the appearance of atypical lymphocytes.
An enterprise-grade SSD with TLC (3b/cell) NAND Flash is presented with three techniques that achieve high speed and high reliability. Quick low-density parity-check (LDPC) reduces the read latency of 1Xnm TLC NAND Flash SSD by 83%. Dynamic V TH optimization and auto data recovery reduce the NAND Flash bit-error rate (BER) by 80% and 18%, respectively. These techniques can be implemented in the SSD controller without circuit overhead. No modification is required to the TLC NAND flash.Enterprise storage demands fast speed and good reliability with high-density for big data applications. Though TLC NAND Flash SSD has the bit cost advantage over MLC (2b/cell) NAND Flash SSD, the adoption in the enterprise market is limited due to its poor speed and reliability. Real-time online analytical processing (OLAP) applications require a quick response from SSD. In real-world workloads, temporal data locality causes read requests to concentrate on the same memory cells. The frequently read data (hot data) suffers from the read disturb while cold data fail due to the data retention. To overcome performance and reliability problems of TLC NAND flash SSD, this paper describes three techniques shown in Fig. 7.7.1.To efficiently correct errors with a short latency, this paper presents quick LDPC. The read latency is 83% lower than advanced error-prediction LDPC (AEP-LDPC) error-correcting code (ECC) [1]. When memory cells wear-out and errors exceed the ECC capability, dynamic V TH optimization adaptively selects the optimal read reference voltage (V Ref ) and increases the V TH read margin. As a result, measured errors are reduced by 80%. Auto data recovery compensates the V TH decrease (the data retention error) with the V TH increase (the read disturb error).First, the LDPC is shown in Fig. 7.7.2. Figure 7.7.3 shows the total read latency and the measured reliability. In the enterprise MLC NAND Flash SSD, fast BCH ECC [2] is used. The error-correction capability of BCH is not sufficient for the enterprise use of TLC NAND Flash because enterprise storage requires higher endurance than consumer storage. The soft-decoding LDPC [3] corrects more errors than BCH ECC. However, it needs analog V TH to calculate the loglikelihood ratio (LLR) and 49-time V Ref sensing is necessary and the read latency increases to 2.3ms. V Ref sensing is defined as sensing a memory cell with one of the reference level. The conventional AEP-LDPC estimates LLR by the harddecision (digital) V TH , the write/erase (W/E) cycle, the retention time and intercell coupling information. Since the analog V TH is not used, the read latency decreases to 1ms. Yet, AEP-LDPC is still 7× slower than BCH ECC. In AEP-LDPC, 21-time V Ref sensing are required to read neighboring cell data in both wordline and bitline directions.To accelerate the read while securing the high reliability, the quick LDPC reads only one of upper/middle/lower pages, corresponding to 2 to 3V Ref sensing. The total read latency is 173μs, which is comparable with the latency of BCH ECC of 146μs. Th...
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.