The shrinking solder dimensions greatly impact the reliability of devices and increase entire failure modes. Limited solder volumes can be consumed completely and transformed into intermetallic compound (IMC) microbumps. Microvoids surface when microbumps are formed and may be attributed to a mismatch of the thermal expansion coefficient between the constituents. After thermal aging at 150 °C, the stress induced by the growth of IMCs relaxes and enhances propagation of the cracks along the middle of the bumps. The brittle nature of the IMC showed minimal resistance to cracks and incurred a failure mode.
In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.
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