Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology

Abstract

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

A Modified Interposer Fabrication Process by Copper Nano-Pillars Filled in Anodic Aluminum Oxide Film for 3D Electronic Package

“…The change from two-dimensional integrated circuits (2D ICs) to 3D ICs is a trend in the electronics industry to break through the limits of very-large-scale integration circuits (VLSI) [1,2]. The interposer structure, which is a crucial part in 3D ICs, has been served as a substrate that can provide a rigid insulating layer between stacked chips and can provide electrical connectivity between layers through the embedded vertical vias [3].…”