A SiC trench MOSFET with an enhanced vertical RESURF effect is proposed and analyzed in this paper. The device features a deep oxide trench surrounded by a P-type doping layer at the source-side. With the assistant depletion effect of the P-type layer, the concentration of the N-drift region is increased and the specific on-resistance (Ron,sp) is thus reduced. The P-type doping can significantly reduce the intensity of the electric field at the gate oxide corner, and modulate the bulk electric field for the device. The breakdown voltage (BV) is therefore improved. As a result, the proposed SiC MOSFET has a better trade-off of BV and Ron,sp. The Ron,sp decreases by 59% and the BV increases by 16% for the proposed device without a CSL layer compared with the conventional trench MOSFET with a CSL layer. Meanwhile, the device exhibits a lower gate-to-drain charge (Qgd) which is reduced by 52% and the switching loss is also reduced by 19%.
A three-dimensional (3D) silicon-carbide (SiC) trench metal–oxide–semiconductor field-effect transistor (MOSFET) with a heterojunction diode (HJD-TMOS) is proposed and studied in this work. The SiC MOSFET is characterized by an HJD which is partially embedded on one side of the gate. When the device is in the turn-on state, the body parasitic diode can be effectively controlled by the embedded HJD, the switching loss thus decreases for the device. Moreover, a highly-doped P+ layer is encircled the gate oxide on the same side as the HJD and under the gate oxide, which is used to lighten the electric field concentration and improve the reliability of gate oxide layer. Physical mechanism for the HJD-TMOS is analyzed. Comparing with the conventional device with the same level of on-resistance, the breakdown voltage of the HJD-TMOS is improved by 23.4%, and the miller charge and the switching loss decrease by 43.2% and 48.6%, respectively.
A novel Silicon-Carbide heterojunction U-MOSFET embedded a P-type pillar buried in the drift layer (BP-TMOS) is proposed and simulated in this study. When functioning in the on state, the merged heterojunction structure will control the parasitic body diode, and the switching loss will decrease. Moreover, to lighten the electric field on the gate oxide corner, a high-doped L-shaped P+ layer near the heterojunction beneath the gate oxide was introduced; thus, the gate oxide reliability improved. A p-type pillar is introduced in the drift layer. The p-type pillar can assistant the drift layer to deplete. Thus, the specific on-resistance for BP-TMOS can be reduced with an increase in the N-drift region’s doping concentration. Compared to the traditional SiC MOSFET (C-TMOS), the specific on-resistance decreased by 20.4%, and the breakdown voltage increased by 53.7% for BP-TMOS, respectively. Meanwhile the device exhibits a 55% decrease and a 69.7% decrease for the switching loss and gate to drain charge.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.