Here, the authors propose a new family of ternary circuits for a general design perspective. Besides presenting an efficient ternary logical circuit approaches, the focus of this study is also about introducing techniques for reducing the performance metric cost of the proposed family. Basic ternary arithmetic gates, ternary half-adder, and ternary partial product generator are also proposed for two different levels. First, direct transistor level implementation is considered, next a modification in the gate level implementation representing a state-of-the-art approach is addressed. Carbon nanotube FET (CNFET) is considered as an appropriate technology for implementation and realisation of ternary circuits. Therefore, simulations are carried out at 32 nm CNFET model using Synopsis HSpice tool. Simulation results show the advantages of ternary structures considering the proposed method.

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Recently multiple valued logic has attracted the attention of digital system designers. Scalable threshold voltage values of carbon nanotube field-effect transistors (CNFETs) can easily be utilised for multiple-V t circuit designs. In this study, a novel energy-efficient method for designing one-digit adder is proposed. The suggested design employ ternary multiplexers to select successor and predecessor of input trits for the output node values. This study describes the novel ternary multiplexer, successor and predecessor cells. The proposed full adder design is evaluated using HSPICE simulation with the standard 32 nm CNFET technology under different operational conditions, including different supply voltages, variation of output load and various operational temperatures. In addition, the sensitivity to process variations of the design is investigated. Finally, the proposed designs are compared with state-of-the-art ternary circuits and based on the simulation results, the proposed full adder cell decreases the power consumption up to 2.3 times lower than the best existing techniques in the literature.

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