Method for designing ternary adder cells based on CNFETs

Abstract

Recently multiple valued logic has attracted the attention of digital system designers. Scalable threshold voltage values of carbon nanotube field-effect transistors (CNFETs) can easily be utilised for multiple-V t circuit designs. In this study, a novel energy-efficient method for designing one-digit adder is proposed. The suggested design employ ternary multiplexers to select successor and predecessor of input trits for the output node values. This study describes the novel ternary multiplexer, successor and predecessor cells. The proposed full adder design is evaluated using HSPICE simulation with the standard 32 nm CNFET technology under different operational conditions, including different supply voltages, variation of output load and various operational temperatures. In addition, the sensitivity to process variations of the design is investigated. Finally, the proposed designs are compared with state-of-the-art ternary circuits and based on the simulation results, the proposed full adder cell decreases the power consumption up to 2.3 times lower than the best existing techniques in the literature.

Carbon Nanotube and Resistive Random Access Memory Based Unbalanced Ternary Logic Gates and Basic Arithmetic Circuits

“…Ternary logic gates were first implemented based on complementary metal oxide semiconductor (CMOS) logic in 1980's however due to the high sensitivity of logic systems to CMOS transistor dimensions, arithmetic logic design utilizing MVL has faced significant challenges in terms of high leakage power, reduced gate control, parameter variation and short channel effect [17]. To seek improvement in MVL circuit designs various emerging technologies such as Carbon Nanotube Field Effect Transistors (CNTFET) [18], Quantum Dot Cellular Automata (QCA) [19], and Single Electron Transistor (SET) [20] have been introduced. However, amongst these technologies, CNTFET has emerged as the standout technologies for the implementation of MVL based designs.…”

Design of ternary logic gates and circuits using GNRFETs

“…In general, the digital calculations are carried out by two‐valued binary logic. In the recent days, ternary logic has gained considerable attraction because of its huge advantages over binary logic such as large bandwidth, reduction of interconnect length, smaller chip area, faster arithmetic, and logical operations [1–3]. In ternary logic, the logic states 0, 1, and 2 represent low, middle, and high, respectively.…”

Novel CNFET ternary circuit techniques for high‐performance and energy‐efficient design

“…The first step in achieving this objective is the efficient design of the basic logic. During the past decade, various designs of basic gates of ternary logic have been published in the literature [13][14][15][16][17][18]. Nonetheless, the very large-scale integration (VLSI) of ternary logic is in its infancy, and introducing new families of high performance and low power is still a great step in the right direction.…”

“…Among the emerging technologies, carbon nanotube FET (CNFET) is the most promising replacement of today silicon‐based FET due to its superior features compared to the other technologies. One of the important characteristics of CNFET is the special ability to adjust the threshold voltage during the manufacturing process [14]. Owing to these benefits, a steady stream of studies about ternary logic hardware realisation has come to fruition.…”