A comprehensive overview of novel high voltage GaN field effect transistors (FETs) based on the Polarization Superjunction (PSJ) concept and a cost-effective approach towards manufacturing these high performance devices are presented. Current challenges impeding wider adoption of GaN power switching transistors in applications, and latest results of scaled-up PSJ-FETs from POWDEC KK, have also been discussed. The article also presents hard-switching characteristics of 400V-to-800V boost converter constructed using a PSJ-FET grown on sapphire substrate and the future direction of GaN power semiconductor technology based on monolithic integration for advanced power electronics.
The hot-carrier degradation mechanism in low-temperature polycrystalline silicon (poly-Si) n-channel lightly doped drain (LDD) thin-film transistors (TFTs) is investigated. The degradation is characterized by transconductance degradation (ÁG m ) at low drain voltage (V d ) and decreases in substrate current (I sub ) and kink current at high V d . It is assumed that the trapped negative charges (acceptor-type trap states) in the gate edge region, mostly outside and partly inside the gate, contribute to hot-carrier degradation after stress under current saturation bias. The degradation presumably first occurs outside the gate in the LDD region and, with increasing stress time, the electron-trapped region expands toward the channel under the gate owing to the saturation of electrons in the trap states. At high-V d bias, a decrease in the lateral electric field in the gate-edge region due to the presence of negative charges reduces I sub and the drain current I d , thereby reducing the kink current. At low-V d bias, the current flow near the upper interface in the gate-edge region decreases after the stress owing to the generated negative charges. The negative charges lead to the decrease in I d in the deep-gate voltage V g region in V g -I d characteristics.
The changes in off-current under on- and off-state stress voltages in n-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are investigated through measurements and simulations. It is found that the off-current increases markedly in the shallow-negative-gate-voltage region and decreases in the deep-gate-voltage region after applying both on- and off-state stresses, resulting in a weaker dependence on negative gate voltage. It can be supposed from the simulations and experiments that the donor-type trap states (positive charges) with a hump-type state profile, located at 0.1–0.2 eV below the midgap, and tail states are generated near the drain junction after applying both stresses. The amount of donor-type states increases in phonon-assisted tunneling with the Pool–Frenkel effect (PAT) and Schockley–Read–Hall generation (SRH) owing to the increase in the deep-trap-state density, and decreases in band-to-band tunneling (BBT) owing to the decrease in electric field, giving rise to a predominant PAT+SRH current in off-current in a wide-negative-gate-voltage region.
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