A two-dimensional electron gas was observed in Zn polar ZnMgO∕ZnO (ZnMgO on ZnO) heterostructures grown by radical source molecular beam epitaxy. The electron mobility of the ZnMgO∕ZnO heterostructures dramatically increased with increasing Mg composition and the electron mobility (μ∼250cm2∕Vs) at RT reached a value more than twice that of an undoped ZnO layer (μ∼100cm2∕Vs). The carrier concentration in turn reached values as high as ∼1×1013cm−2 and remained nearly constant regardless of Mg composition. Strong confinement of electrons at the ZnMgO∕ZnO interface was confirmed by C-V measurements with a concentration of over 4×1019cm−3. Temperature-dependent Hall measurements of ZnMgO∕ZnO heterostructures also exhibited properties associated with well defined heterostructures. The Hall mobility increased monotonically with decreasing temperature, reaching a value of 2750cm2∕Vs at 4K. Zn polar “ZnMgO on ZnO” structures are easy to adapt to a top-gate device. These results open new possibilities for high electron mobility transistors based upon ZnO-based materials.
We proposed a two-dimensional (2-D) physical model of n-channel polycrystalline silicon (poly-Si) single drain (SD) and lightly-doped drain (LDD) thin film transistor (TFT) to analyze hot-carrier degradation. The model is based on a 2-D device simulator's Gaussian doping profiles for the source and drain junctions fitted to the lateral and vertical impurity profiles in poly-Si obtained from a 2-D process simulator. It is found that, for current saturation bias, the maximum 2-D lateral electric field is located in the deep drain region under the gate, and the current flows in the deep channel region near the drain junction. In poly-Si n-channel TFTs, it was predicted from our 2-D device simulation that the generation of both band-tail states in poly-Si and interface states at both interfaces can contribute to hot-carrier degradation. We have shown that, in the case of n-channel SD TFTs, generated band-tail states greatly affect drain avalanche hot-carrier (DAHC) degradation for longer stress time of 10,000 s.
Hot-carrier effect in low-temperature n-channel polycrystalline silicon (poly-Si) lightly doped drain (LDD) thin-film transistors (TFTs) for various n À doping concentrations was examined by using a two-dimensional (2D) device simulation. It was found that, in the case of a low n À doping concentration for a high applied gate voltage, large potential drops appeared at the source side and the drain side. This was because of the reduced potential drop in the channel region, giving rise to a high lateral field and an impact ionization rate at both the source and the drain sides. These results suggested that the hot-carrier degradation due to avalanche hot-carriers occurred at both the source and the drain sides in a high-applied-gate-voltage region in the case of a low n À doping concentration, while, in the case of low gate voltage, the degradation occurred at only the high-field drain side. Therefore, the n À doping concentration should be optimized to minimize the hotcarrier degradation in the source side and the drain side.
The hot-carrier degradation mechanism in low-temperature polycrystalline silicon (poly-Si) n-channel lightly doped drain (LDD) thin-film transistors (TFTs) is investigated. The degradation is characterized by transconductance degradation (ÁG m ) at low drain voltage (V d ) and decreases in substrate current (I sub ) and kink current at high V d . It is assumed that the trapped negative charges (acceptor-type trap states) in the gate edge region, mostly outside and partly inside the gate, contribute to hot-carrier degradation after stress under current saturation bias. The degradation presumably first occurs outside the gate in the LDD region and, with increasing stress time, the electron-trapped region expands toward the channel under the gate owing to the saturation of electrons in the trap states. At high-V d bias, a decrease in the lateral electric field in the gate-edge region due to the presence of negative charges reduces I sub and the drain current I d , thereby reducing the kink current. At low-V d bias, the current flow near the upper interface in the gate-edge region decreases after the stress owing to the generated negative charges. The negative charges lead to the decrease in I d in the deep-gate voltage V g region in V g -I d characteristics.
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