International audienceIn this paper, we discuss scheduling problems in semiconductor manufacturing. Starting from describing the manufacturing process, we identify typical scheduling problems found in semiconductor manufacturing systems. We describe batch scheduling problems, parallel machine scheduling problems, job shop scheduling problems, scheduling problems with auxiliary resources, multiple orders per job scheduling problems, and scheduling problems related to cluster tools. We also present important solution techniques that are used to solve these scheduling problems by means of specific examples, and report on known implementations. Finally, we summarize some of the challenges in scheduling semiconductor manufacturing operations

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In this chapter, we discuss production planning approaches for semiconductor manufacturing. Planning is on the highest level of the PPC hierarchy. Planning approaches provide important input for the order release schemes discussed in Chap. 6. We start by describing short-term planning approaches. Spreadsheet modeling and simulation are used in this situation.Then, we continue by describing master planning approaches in semiconductor manufacturing. They are used to assign production quantities to different facilities in different periods of time for a horizon of several months. Weekly time periods are considered. Simulation-based performance assessment of master planning approaches is briefly discussed. Next, we discuss capacity planning approaches. In contrast to master planning, these approaches deal with a longer planning horizon and monthly time periods. We discuss only deterministic planning approaches for master and capacity planning. Then, we present enterprise-wide planning approaches. In this situation, we consider a planning horizon of several years and quarters as periods. We also deal with the question of whether or not it is beneficial to open new facilities. Deterministic and stochastic settings are described for enterprise-wide planning problems.One typical assumption in planning approaches is a fixed CT; however, the CT is load-dependent. Therefore, we discuss different possibilities to model load-dependent CT within planning approaches. We consider CT-TP curves, iterative simulation, and finally clearing functions. Short-Term Capacity PlanningIn this section, we start by discussing the motivation of spreadsheet-based and simulation-based short-term capacity planning. We then make the first approach more concrete for wafer fabs. Spreadsheet-based short-term capacity planning approaches are discussed for back-end facilities. Finally, short-term capacity planning based on discrete-event simulation is described.

The highly competitive electronics manufacturing marketplace demands that suppliers provide low-cost, high-quality products to their customers in a timely fashion. Shortened product life cycles and increasingly global competition have caused traditional manufacturers to focus on their company core competencies, such as product design and development, choosing to outsource the actual manufacturing of their products to contract manufacturers. Although the decision to outsource can have both positive and adverse effects on key areas of the manufacturing supply chain, one positive effect is that the manufacturer's supply chain agility is increased. Outsourcing has caused an increase in the amount of information that is shared between supply chain partners. As a result, a greater reliance on suppliers and alliance partners has become essential for company survival. We examine the ways in which contract manufacturing has increased the agility of the electronics manufacturing supply chain. T h e res ea rc h re g ister fo r th is jo u rn a l is a v a ila b le a t http://www.emeraldinsight.com/researchregisters T h e c u rre n t is su e a n d fu ll te x t a rc h iv e o f th is jo u rn a l is a v a ila b le a t http://www.emeraldinsight.com/0960-0035.htm This research effort was supported by Avaya Incorporated (www.avaya.com) through the Logistics Institute (www.tli.uark.edu) at the University of Arkansas.

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SUMMARYIncreases in the demand for integrated circuits have highlighted the importance of meeting customer quality and on-time delivery expectations in the semiconductor industry. A modiÿed shifting bottleneck heuristic is developed for minimizing the total weighted tardiness in a semiconductor wafer fabrication facility. This 'complex' job shop is characterized by re-entrant or re-circulating product ow through a number of di erent tool groups (one or more machines operating in parallel). These tool groups typically contain batching machines, as well as machines that are subject to sequence-dependent setups. The disjunctive graph of the complex job shop is presented, along with a description of the proposed heuristic. Preliminary results indicate the heuristic's potential for promoting on-time deliveries by semiconductor manufacturers for their customers' orders.

While logistics research recently has placed increased focus on disruption management, few studies have examined the response and recovery phases in post-disaster operations. We present a multiple objective, integrated network optimisation model for making strategic decisions in the supply distribution and network restoration phases of humanitarian logistics operations. Our model provides an equity-based solution for constrained capacity, budget and resource problems in post-disaster logistics management. We conduct designed experiments for this NP-hard problem to analyse important aspects of the integrated problem for both small-and large-sized networks: full vs. partial restoration and pooled vs. separate budgeting approach. Finally, we apply the model to a Hazus-generated regional case study based on an earthquake scenario and generate efficient Pareto frontiers to understand the trade-off between the objectives of interest.

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