A modified shifting bottleneck heuristic for minimizing total weighted tardiness in complex job shops

Abstract

SUMMARYIncreases in the demand for integrated circuits have highlighted the importance of meeting customer quality and on-time delivery expectations in the semiconductor industry. A modiÿed shifting bottleneck heuristic is developed for minimizing the total weighted tardiness in a semiconductor wafer fabrication facility. This 'complex' job shop is characterized by re-entrant or re-circulating product ow through a number of di erent tool groups (one or more machines operating in parallel). These tool groups typically contain batching machines, as well as machines that are subject to sequence-dependent setups. The disjunctive graph of the complex job shop is presented, along with a description of the proposed heuristic. Preliminary results indicate the heuristic's potential for promoting on-time deliveries by semiconductor manufacturers for their customers' orders.

Simulation Model for Job Shop Production Process Improvement in Machine Parts Manufacturing

“…The traditional job shops had greater performance in variable concerned with queue. Besides, the simulation tools were applied with optimization method to solve the real-world scheduling problem, such as modified shifting bottleneck heuristic, Mason et al [7], tabu search algorithm and etc. Many research presented the great benefits of the simulation tools to assist in performance improving, problems solving, including a great help in decision making.…”

Operational planning and control of semiconductor wafer production

“…However, there is very little theoretical research to analyze and solve such problems with the notable exceptions of Mason et al (2002), Mason et al (2004) and Mason et al (2005). Therefore, the development of models and solution procedures for solving re-entrant flowshop scheduling problems involving large number of machines would enhance the effectiveness and efficiency of semiconductor wafer production.…”

A Batch Optimization Solver for Diffusion Area Scheduling in Semiconductor Manufacturing

“…The considered problem can be seen as an extension of the job-shop problem and, consequently, the disjunctive graph model can be used for batching and scheduling problems as proposed by [MFC02]. In their article, the authors consider a different objective function (namely total weighted tardiness).…”

“…In [ICS + 03] and [MH03], the authors propose to use a dispatching rule to batch the operations and a genetic algorithm to assign the batches to equipment. In [MFC02], a scheduling problem in semiconductor manufacturing related to the one tackled in this paper is solved by a modified shifting bottleneck heuristic [ABZ88].…”

“…In this paper, we propose to model solutions of the considered batching and scheduling problem through a variant of the disjunctive graph proposed in [MFC02]. A constructive heuristic is designed that builds an initial solution as well as improvement procedures based on local search and simulated annealing.…”