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<span lang="EN-US">Advanced Encryption Standard (AES) adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES), as the most widely used encryption algorithm in many security applications. Up to today, AES standard has key size variants of 128, 192, and 256-bit, where longer bit keys provide more secure ciphered text output. In the hardware perspective, bigger key size also means bigger area and small throughput. Some companies that employ ultra-high security in their systems may look for a key size bigger than 128-bit AES. In this paper, 128, 192 and 256-bit AES hardware are implemented and compared in terms of throughput and area. The target hardware used in this paper is Virtex XC5VLX50 FPGA from Xilinx. Total area and Throughput results are presented and graphically compared.</span>

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In the present paper we present an architecture to implement Advanced Encryption Standard (AES) Rijndael algorithm in reconfigurable hardware. Rijndael algorithm is the new AES adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES). Compared to software implementation, hardware implementation of Rijndael algorithm provides more physical security as well as higher speed. The first factor to be considered on implementing AES is the application. High-speed designs are not always desired solutions. In some applications, such as mobile computing and wireless communications, smaller throughput is demanded. Architecture presented uses memory modules (i.e., Dual-Port RAMs) of Field-Programmable Gate Array (FPGAs) for storing all the results of the fixed operations (i.e., Look-Up Table ), and Digital Clock Manager (DCM) that we used effectively to optimize the execution time, reduce design area and facilitates implementation in FPGA. The architecture consumes only 326 slices plus 3 Block Random Access Memory (BRAMs). The throughput obtained was of 270 Mbits/s. The target hardware used in this paper is Spartan XC3S500E FPGA from Xilinx. Results are presented and compared with other reference implementations, as known from the technical literature. The presented architecture can be used in a wide range of embedded applications.

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Satellite remote sensing (SRS) needs to make use of up-to-date technology. The trend in SRS missions has always been towards using hardware devices with smaller size, lower cost, more flexibility, and higher computational power. Therefore, Field Programmable Gate Array (FPGA) technology is highly used by the scientific community and hardware developers to implement different SRS algorithms. Thus, FPGAs offer well-suited architectural features; large number of programmable logic elements, distributed and block RAMs, DSP and register slices and look up tables. This paper describes an approach to the implementation of the Land Surface Temperature Split-Window (LST-SW) algorithm structure based on FPGA technology.

Recently, convolutional neural networks have grown in popularity in a variety of fields, such as computer vision and audio and text processing. This importance is due to the performance of this type of neural network in the state of the art, and in a wide variety of disciplines. However, the use of convolutional neural networks has not been widely used for remote sensing applications until recently. In this paper, we propose a CNN-based system capable of efficiently extracting buildings from very high-resolution satellite images, by combining the performances of the two architectures; U-Net and VGG19, which is obtained by putting two blocks in parallel based mainly on U-Net: The first block is a standard U-Net, and the second is designed by replacing the contraction path of standard U-Net with the pre-trained weights of VGG19.

Transmission of sensitive data in space missions and particularly in satellite remote sensing to the ground station is exposed to multiple threats impacting the confidentiality of data, access unauthorized to the satellite system, in addition, the space environment causes several threats that can affect the hardware of satellites. This paper describes an improved approach to implement a secure Land Surface Temperature-Split Windows (LST-SW) algorithm based on the Advanced Encryption Standard using the Reconfigurable Dynamic Method for application on-board earth observation satellites implemented on radiation-tolerant Virtex-4QV FPGA. The experimental results showed that the proposed hardware secure implementation of the LST-SW algorithm using Xilinx Virtex-4QV FPGA achieves higher throughput of 907.644 Mbps sufficient for satellite remote sensing mission. Moreover, the suggested implementation consumes 4089 Slices and 4 BRAMs. Finally, the authors use security measurement analyses to verify the safety and performance of the proposed encryption LST-SW module.