Electromigration results for a 264 sample electromigration study performed on dual damascene copper interconnects are presented and reviewed. The stress results show multi-modal failure distributions and extensive failure analysis provides possible explanations as to the failure modes. Monte-carlo 'ype simulations are used to investigate the statistical implications of using hi-modal fitting to predict reliability performance.
ATTENDANCE could be used to effectively measure reliability of a fa.b's products. Representatives of the FSA were present to respond to questions and to clarify objectives of the project. After the discussion, the consensus of the groups was thatThe WLR discussion group was well-attended, averaging approximately 25 persons per night. As expected, some lively discussion ensued from these groups, which represented many different facets of the semiconductor industry. QUESTIONS TO THE ATTENDEESAn informal questionnaire was used as a tool to sample the opinions of attendees on several fronts. Results were quickly tabulated during the initial discussion and then used as the basis for plenty of further discussion. The questionnaire is reproduced in Appendix I. Definition of WLRThe first section asked participants to express their opinion about the basic definition of "Wafer Level Reliability (WLR)" (see Appendix 1).The responses indicated that two sets of opinions existed. One set said that WLR refers to all tests which have an impact on reliability while the product is still in the wafer form, and this includes stressing of test die on product, stressing the product itself on product wafers, stressing test wafers, and non-electrical measurements on all types of wafers. (Examples of the latter include wafer bow and metal reflectivity.) The second "set" of opinions regarding a WLR definition took a more focused point of view and said that it includes only electrical stress tests. This opinion seemed to be held by fewer of the participants compared to the broader definition. Standardized WLRThe second portion of the questionnaire referred to a project being undertaken by the Fabless Semiconductor Association (FSA). The first phase of the project is to promote the use of WLR in semiconductor foundry fabs by collecting wafer-level reliability data from member foundries and issuing FSA certification to these fabs. The second phase of the project is to develop a suite of standardized test structures for a 0.25 pm technology. These structures could be used in conjunction with WLR in member fabs and thereby allow design shops to compare one fab to another. Attendees were asked their opinions of this in the form of questions d to h (see Appendix 1).There was considerable discussion about the efficacy of standardized structures, followed by the question of whether the results of WLR 1). Present WLR tests are not able to compare fabs and technologies.2). Test structures and test methodologies need to be standardized, but with changing technologies, the structures and methodologies will also need to be continuously updated. WLR ConfidenceThe final portion of the questionnaire yielded some very interesting and telling results. For this section, attendees were asked to simply list those WLR tests in which they had confidence, those in which they had some confidence, and those in which they had no confidence.A large number of individual wafer-level reliability stresses were listed overall, including time-dependent dielectric breakdown...
In this study, we have subjected an aged (stress voided) line/stud test structure to a stepped current at ambient temperature until the structure failed due to Joule-heating-induced thermal runaway. During the current stepping, resistance was also measured at a low current of 1 mA, which was applied periodically to monitor possible structural changes in the line. The resistance vs. monitor-current and the resistance vs. stepped-current measurements demonstrate interesting systematic decreases in resistance on a number of chips. Whether these decreases occur or not appears to be a function of initial damage induced during aging. It is postulated that the stepped-current resistance measurements are influenced by the presence of a flat void or thin crack associated with a stud, while the monitor-current resistance healing is influenced by the redistribution of Al(Cu) into a preexisting void in the line.
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