Investigation of via-dominated multi-modal electromigration failure distributions in dual damascene Cu interconnects with a discussion of the statistical implications

Abstract

Electromigration results for a 264 sample electromigration study performed on dual damascene copper interconnects are presented and reviewed. The stress results show multi-modal failure distributions and extensive failure analysis provides possible explanations as to the failure modes. Monte-carlo 'ype simulations are used to investigate the statistical implications of using hi-modal fitting to predict reliability performance.

Statistical Analysis of Electromigration Lifetimes and Void Evolution for Cu Interconnects

“…Furthermore, Figure 6.14 seems to indicate that the distribution corresponding to DD samples deviates from the straight line in the lognormal plot for small percentage values suggesting an early failure population of about 6%. These data points are most likely due to void formation in the via, which requires only a small void to fail the line as discussed in several publications [for instance : Ogawa 2001, Ogawa 2002a, Gill 2002, Lai 2001. However, they prohibit fitting a monomodal distribution to the measured data to obtain the median and sigma values.…”

Effect of test condition and stress free temperature on the electromigration failure of Cu dual damascene submicron interconnect line-via test structures

“…In the M2 test of Cu DD structure, the reported failure sites are Site-A, Site-B, Site-C, and in the M1 test, Site-D is reported [1,[7][8][9][10][11][12][13]. A closer examination on these failure site reveals that neither current crowding nor the metallization stress state alone can explain the reason of such failure locations [14][15].…”

“…The dual damascene (DD) process for the copper interconnection system has resulted in several significant changes in the electromigration (EM) behaviors of the interconnection [1,2]. These changes are the following.…”

Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links

“…An open-wire fault is becoming a critical issue in current and future technology nodes where a total interconnection length in a single chip is in kilometer order and it continues to increase [1]. Even a single open-wire fault in the link by electromigration [22] causes fatal errors in a whole system [23].…”