We report a programmable analog bionic ear (cochlear implant) processor in a 1.5-microm BiCMOS technology with a power consumption of 211 microW and 77-dB dynamic range of operation. The 9.58 mm x 9.23 mm processor chip runs on a 2.8 V supply and has a power consumption that is lower than state-of-the-art analog-to-digital (A/D)-then-DSP designs by a factor of 25. It is suitable for use in fully implanted cochlear-implant systems of the future which require decades of operation on a 100-mAh rechargeable battery with a finite number of charge-discharge cycles. It may also be used as an ultra-low-power spectrum-analysis front end in portable speech-recognition systems. The power consumption of the processor includes the 100 microW power consumption of a JFET-buffered electret microphone and an associated on-chip microphone front end. An automatic gain control circuit compresses the 77-dB input dynamic range into a narrower internal dynamic range (IDR) of 57 dB at which each of the 16 spectral channels of the processor operate. The output bits of the processor are scanned and reported off chip in a format suitable for continuous-interleaved-sampling stimulation of electrodes. Power-supply-immune biasing circuits ensure robust operation of the processor in the high-RF-noise environment typical of cochlear implant systems.

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Fast wideband spectrum analysis is expensive in power and hardware resources. We show that the spectrum-analysis architecture used by the biological cochlea is extremely efficient: analysis time, power and hardware usage all scale linearly with , the number of output frequency bins, versus log() for the Fast Fourier Transform. We also demonstrate two on-chip radio frequency (RF) spectrum analyzers inspired by the cochlea. They use exponentially-tapered transmission lines or filter cascades to model cochlear operation: Inductors map to fluid mass, capacitors to membrane stiffness and active elements (transistors) to active outer hair cell feedback mechanisms. Our RF cochlea chips, implemented in a 0.13 m CMOS process, are 3 mm 1.5 mm in size, have 50 exponentially-spaced output channels, have 70 dB of dynamic range, consume 300 mW of power and analyze the radio spectrum from 600 MHz to 8 GHz. Our work, which delivers insight into the efficiency of analog computation in the ear, may be useful in the front ends of ultra-wideband radio systems for fast, power-efficient spectral decomposition and analysis. Our novel rational cochlear transfer functions with zeros also enable improved audio silicon cochlea designs with sharper rolloff slopes and lower group delay than prior all-pole versions.

We report a 75-dB 2.8-W 100-Hz-10-kHz envelope detector in a 1.5m 2.8-V CMOS technology. The envelope detector performs input dc insensitive voltage-to-current converting rectification followed by novel nanopower current-mode peak detection. The use of a subthreshold wide linear range transconductor allows greater than 1.7pp input voltage swings. We show theoretically that the optimal performance of this circuit is technology independent for the given topology and may be improved only by spending more power due to thermal noise rectification limits. A novel circuit topology is used to perform 140-nW peak detection with controllable attack and release time constants. We demonstrate good agreement of experimentally measured results with theory. The envelope detector is useful in low-power bionic implants for the deaf, hearing aids, and speech-recognition front-ends.