We report a programmable analog bionic ear (cochlear implant) processor in a 1.5-microm BiCMOS technology with a power consumption of 211 microW and 77-dB dynamic range of operation. The 9.58 mm x 9.23 mm processor chip runs on a 2.8 V supply and has a power consumption that is lower than state-of-the-art analog-to-digital (A/D)-then-DSP designs by a factor of 25. It is suitable for use in fully implanted cochlear-implant systems of the future which require decades of operation on a 100-mAh rechargeable battery with a finite number of charge-discharge cycles. It may also be used as an ultra-low-power spectrum-analysis front end in portable speech-recognition systems. The power consumption of the processor includes the 100 microW power consumption of a JFET-buffered electret microphone and an associated on-chip microphone front end. An automatic gain control circuit compresses the 77-dB input dynamic range into a narrower internal dynamic range (IDR) of 57 dB at which each of the 16 spectral channels of the processor operate. The output bits of the processor are scanned and reported off chip in a format suitable for continuous-interleaved-sampling stimulation of electrodes. Power-supply-immune biasing circuits ensure robust operation of the processor in the high-RF-noise environment typical of cochlear implant systems.
Large dc blocking capacitors are a bottleneck in reducing the size and cost of neural implants. We describe an electrode-stimulator chip that removes the need for large dc blocking capacitors in neural implants by achieving precise charge-balanced stimulation with <6 nA of dc error. For cochlear implant patients, this is well below the industry's safety limit of 25 nA. Charge balance is achieved by dynamic current balancing to reduce the mismatch between the positive and negative phases of current to 0.4%, followed by a shorting phase of at least 1 ms between current pulses to further reduce the charge error. On +6 and -9 V rails in a 0.7-mum AMI high voltage process, the power consumption of a single channel of this chip is 47 muW when biasing power is shared by 16 channels.
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