Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuitfsystem. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining [l], lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL) [2], modeled after CPL [3], to achieve equal delay along all the propagation paths in the logic structure. An 8 x 8 b multiplier is designed using this logic in a 0 . 8~ technology. The carrysave multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm x 0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well.Zndex Terms-High performance multiplier macrocell, high throughput arithmetic unit, VLSI multipliers, wave pipelined multiplier, wave pipelining in CMOS technology.
An ad hoc network is composed of mobile nodes without any infrastructure. Mobile nodes self organize themselves to form a network over radio links. The trend of applications of mobile ad hoc networks requires increased group oriented services. Hence multicast support is critical for ad hoc networks. As the number of participating nodes increase, scalability becomes an important issue. On Demand Multicast Routing Protocol (ODMRP) [1] provides high Packet Delivery Ratio in presence of high mobility. But ODMRP suffers from higher control overhead as the network size and the number of source nodes increase.In this paper, we present an efficient hybrid multicast routing protocol suitable for high mobility applications and it addresses the scalability issue of ODMRP protocol. This protocol separates out data forwarding path from joinquery forwarding path. We incorporate low overhead local clustering technique to classify all nodes into core and normal categories. When multicast routes to destination nodes are unavailable, join-query messages are sent to all nodes in the network and data packets are forwarded by the core nodes to the destination nodes using Differential Destination Multicast [2]. Through simulations we show that this protocol reduces control overhead and increases packet delivery ratio by 20-50% for different network scenarios. 1
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