An ad hoc network is composed of mobile nodes without any infrastructure. Mobile nodes self organize themselves to form a network over radio links. The trend of applications of mobile ad hoc networks requires increased group oriented services. Hence multicast support is critical for ad hoc networks. As the number of participating nodes increase, scalability becomes an important issue. On Demand Multicast Routing Protocol (ODMRP) [1] provides high Packet Delivery Ratio in presence of high mobility. But ODMRP suffers from higher control overhead as the network size and the number of source nodes increase.In this paper, we present an efficient hybrid multicast routing protocol suitable for high mobility applications and it addresses the scalability issue of ODMRP protocol. This protocol separates out data forwarding path from joinquery forwarding path. We incorporate low overhead local clustering technique to classify all nodes into core and normal categories. When multicast routes to destination nodes are unavailable, join-query messages are sent to all nodes in the network and data packets are forwarded by the core nodes to the destination nodes using Differential Destination Multicast [2]. Through simulations we show that this protocol reduces control overhead and increases packet delivery ratio by 20-50% for different network scenarios. 1
An integrated digital controller design for dc-dc converter is proposed in this paper. The proposal presents a multipleband dual-stage (MBDS) delay line A/D converter (ADC) for wide dynamic range of operation with reduced ripple, chip area, and power consumption. This proposal also introduces a novel folding logic for digital error calculation and dual-mode error control PID for improving transient response. A complete closed-loop experimental prototype is demonstrated on a field-programmable-gatearray-based setup. The feasibility and functionality of the proposed digital controller is verified with a closed-loop synchronous buck converter prototype that switches at 1 MHz and regulates over a wide output voltage range of 1.6-3.3 V. The proposed MBDS delay line ADC is fabricated with discrete logic gates and flip-flops. The integrated digital controller is also implemented using standard cell-based design methodology in 0.5-µm CMOS technology. The design reduces 33% on-chip area compared to an equivalent of 64 tap delay line ADC. The complete digital controller chip takes less than 0.7 mm 2 of silicon area and consumes an average current of 92 µA at 1-MHz switching frequency. The voltage-mode digital loop achieves tracking time of less than 10 µs for 1-V step change of the reference voltage and settling time of 20 µs. Postlayout simulation and experimental results are demonstrated.Index Terms-Analog-to-digital converter, dc-dc converter, delay line ADC, dynamic voltage scaling, piecewise linear, wide dynamic range.
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