Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions

“…This has led researchers to propose management techniques such as Vantage [31] that target high-associativity cache structures such as z-caches [32] and molecular caches [33]. Such cache structures add non-negligible complexity compared to conventional set-associative caches which implies that they are challenging to design, verify and deploy in commercial processors [34].…”

Section: Shared Cache Management Case Studymentioning

confidence: 99%

GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime

Jahre

Eeckhout

2018

2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Abstract-Multi-core memory systems commonly share resources between processors. Resource sharing improves utilization at the cost of increased inter-application interference which may lead to priority inversion, missed deadlines and unpredictable interactive performance. A key component to effectively manage multi-core resources is performance accounting which aims to accurately estimate interference-free application performance. Previously proposed accounting systems are either invasive or transparent. Invasive accounting systems can be accurate, but slow down latency-sensitive processes. Transparent accounting systems do not affect performance, but tend to provide less accurate performance estimates.We propose a novel class of performance accounting systems that achieve both performance-transparency and superior accuracy. We call the approach dataflow accounting, and the key idea is to track dynamic dataflow properties and use these to estimate interference-free performance. Our main contribution is Graph-based Dynamic Performance (GDP) accounting. GDP dynamically builds a dataflow graph of load requests and periods where the processor commits instructions. This graph concisely represents the relationship between memory loads and forward progress in program execution. More specifically, GDP estimates interference-free stall cycles by multiplying the critical path length of the dataflow graph with the estimated interference-free memory latency. GDP is very accurate with mean IPC estimation errors of 3.4% and 9.8% for our 4-and 8-core processors, respectively. When GDP is used in a cache partitioning policy, we observe average system throughput improvements of 11.9% and 20.8% compared to partitioning using the state-of-the-art Application Slowdown Model.

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“…Varadarajan et al in [Varadarajan et al 2006] propose the idea of "molecular caches": CPU caches that are organized as a series of molecules. In this architecture, molecules are small in size (8-32KB) and reflect the structure of a direct-mapped cache.…”

Section: Average-case Performancementioning

confidence: 99%

A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

et al. 2015

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Multicore processors are being extensively used by real-time systems, mainly because of their demand for increased computing power. However, multicore processors have shared resources that affect the predictability of real-time systems, which is the key to correctly estimate the worst-case execution time of tasks. One of the main factors for unpredictability in a multicore processor is the cache memory hierarchy. Recently, many research works have proposed different techniques to deal with caches in multicore processors in the context of real-time systems. Nevertheless, a review and categorization of these techniques is still an open topic and would be very useful for the real-time community. In this article, we present a survey of cache management techniques for real-time embedded systems, from the first studies of the field in 1990 up to the latest research published in 2014. We categorize the main research works and provide a detailed comparison in terms of similarities and differences. We also identify key challenges and discuss future research directions.

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Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions

Cited by 46 publications

References 9 publications

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime

A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

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