A modified merged capacitor switching (MCS) scheme is proposed for the successive approximation register (SAR) analogue-to-digital converter (ADC). The conventional MCS technique previously applied to a pipelined ADC improves signal processing speed and, with use in the SAR ADC, this scheme achieves lowest switching energy among existing switching schemes. The MCS scheme achieves 93.4% less switching energy as compared to the conventional architecture.

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A calibrated 10 b 5 MS/s 28 nm CMOS successive-approximationregister ADC based on an integer-based split capacitor array is presented. The proposed ADC employs a split capacitor array to optimise the overall power consumption, chip area and linearity performance. An attenuation capacitor between two capacitor arrays is implemented with an integer multiple of unit capacitors rather than a fraction of unit capacitors. The proposed calibration of capacitors reduces the non-linearity error caused by device mismatches in the conventional split capacitor array. The measured prototype ADC which has an active die area of 0.063 mm 2 shows a maximum signal-to-noise-anddistortion ratio and spurious-free dynamic range of 59.25 and 70.44 dB, respectively, and consumes 42.5 μW at 0.7 V and 5 MS/s. Moreover, the measured differential non-linearity (NL) and integral NL are within 0.36 and 0.52 least significant bit, respectively, after calibration.

A 12 b 50 MS/s successive-approximation register (SAR) ADC with a highly linear C-R hybrid DAC is presented. The proposed DAC significantly reduces the required total number of unit capacitors by processing the upper bits based on a binary-weighted capacitor array and the remaining lower bits based on reference segment voltages, which are obtained from a simple resistor string. The reduced number of unit capacitors enables the use of larger unit capacitance, resulting in improved matching accuracy. In the C-R hybrid DAC, an input range scaling technique, which matches a full-scale input range to the reference voltage range, implements the binary-weighted SAR operation without additional capacitors and reference voltages. The DAC linearity is improved considerably through the processinsensitive capacitor-array layout, which cancels out oxide-gradient errors. The prototype ADC in a 0.18 μm CMOS process demonstrates measured differential and integral non-linearities within 0.71 LSB and 0.85 LSB at 12 b, respectively, with a maximum signal-to-noise-anddistortion ratio and a spurious-free dynamic range of 64.3 and 74.7 dB at 50 MS/s, respectively. The ADC occupies an active die area of 0.17 mm 2 and consumes 2.63 mA with a 1.8 V supply voltage.